LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 353
LM3S2965-IQN25-A0T
Manufacturer Part Number
LM3S2965-IQN25-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IQN25-A0T.pdf
(542 pages)
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SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x020
Type W1C, reset 0x0000.0000
June 04, 2007
Reset
Reset
Type
Type
Bit/Field
31:2
1
0
RO
RO
31
15
0
0
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
RO
RO
30
14
0
0
reserved
RORIC
Name
RTIC
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
W1C
W1C
Type
27
11
0
0
RO
RO
RO
26
10
0
0
Reset
0
0
0
RO
RO
25
0
9
0
reserved
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Receive Time-Out Interrupt Clear
0: No effect on interrupt.
1: Clears interrupt.
SSI Receive Overrun Interrupt Clear
0: No effect on interrupt.
1: Clears interrupt.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S2965 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RTIC
W1C
RO
17
0
1
0
RORIC
W1C
RO
16
0
0
0
353
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