LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 266
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LM3S2965-IQN25-A0T
Manufacturer Part Number
LM3S2965-IQN25-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IQN25-A0T.pdf
(542 pages)
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Analog-to-Digital Converter (ADC)
ADC Raw Interrupt Status (ADCRIS)
Base 0x4003.8000
Offset 0x004
Type RO, reset 0x0000.0000
266
Reset
Reset
Type
Type
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004
This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits
may be polled by software to look for interrupt conditions without having to generate controller
interrupts.
RO
RO
30
14
0
0
reserved
Name
INR3
INR2
INR1
INR0
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
reserved
Reset
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Set by hardware when a sample with its respective ADCSSCTL3 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN3 bit.
Set by hardware when a sample with its respective ADCSSCTL2 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN2 bit.
Set by hardware when a sample with its respective ADCSSCTL1 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN1 bit.
Set by hardware when a sample with its respective ADCSSCTL0 IE bit
has completed conversion. This bit is cleared by writing a 1 to the
ADCISC IN0 bit.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
INR3
RO
RO
19
0
3
0
INR2
RO
RO
18
0
2
0
June 04, 2007
INR1
RO
RO
17
0
1
0
INR0
RO
RO
16
0
0
0
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