LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 494
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LM3S2965-IQN25-A0T
Manufacturer Part Number
LM3S2965-IQN25-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IQN25-A0T.pdf
(542 pages)
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Quadrature Encoder Interface (QEI)
QEI Control (QEICTL)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x000
Type R/W, reset 0x0000.0000
494
Reset
Reset
Type
Type
Bit/Field
31:13
8:6
12
11
10
9
5
4
RO
RO
31
15
0
0
Register 1: QEI Control (QEICTL), offset 0x000
This register contains the configuration of the QEI module. Separate enables are provided for the
quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in
order to capture the velocity, but the velocity does not need to be captured in applications that do
not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset
mode, and velocity predivider are all set via this register.
reserved
RO
RO
30
14
0
0
STALLEN
ResMode
reserved
VelDiv
Name
VelEn
INVB
INVA
INVI
RO
RO
29
13
0
0
STALLEN
R/W
RO
28
12
0
0
INVI
R/W
RO
Type
27
11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
RO
INVB
R/W
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
0
INVA
R/W
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When set, the QEI stalls when the microcontroller asserts Halt.
When set , the input Index Pulse is inverted.
When set, the PhB input is inverted.
When set, the PhA input is inverted.
A predivider of the input quadrature pulses before being applied to the
QEICOUNT accumulator. This field can be set to the following values:
When set, enables capture of the velocity of the quadrature encoder.
The Reset mode for the position counter. When 0, the position counter
is reset when it reaches the maximum; when 1, the position counter is
reset when the index pulse is captured.
R/W
RO
Binary Value
24
0
8
0
reserved
000
001
010
011
100
101
110
111
VelDiv
R/W
RO
23
0
7
0
Predivider
R/W
RO
÷128
22
0
6
0
÷16
÷32
÷64
÷1
÷2
÷4
÷8
VelEn
R/W
RO
21
0
5
0
ResMode
R/W
RO
20
0
4
0
CapMode
R/W
RO
19
0
3
0
SigMode
R/W
RO
18
0
2
0
June 04, 2007
Swap
R/W
RO
17
0
1
0
Enable
R/W
RO
16
0
0
0
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