LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 152

• Manufacturer Part Number: LM3S2965-IQN25-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Internal Memory
User Debug (USER_DBG)
Base 0x400F.E000
Offset 0x1D0
Type R/W
152
Reset
Reset
Type
Type
Bit/Field
30:3
31
2
1
0
N O T W R I T T E N
R/W
R/W
31
15
1
1
Register 10: User Debug (USER_DBG), offset 0x1D0
Note:
This register provides a write-once mechanism to disable external debugger access to the device
in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory
and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0
disables any external debugger access to the device permanently, starting with the next power-up
cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written
and is controlled through hardware to ensure that the register is only written once.
R/W
R/W
30
14
1
1
NOTWRITTEN
Name
DBG1
DBG0
DATA
INIT1
Offset is relative to System Control base address of 0x400FE000.
R/W
R/W
29
13
1
1
R/W
R/W
28
12
1
1
R/W
R/W
Type
27
11
R/W
R/W
R/W
R/W
R/W
1
1
R/W
R/W
26
10
1
1
0xFFFFFFF
Reset
1
1
1
0
DATA
R/W
R/W
25
1
9
1
Preliminary
Description
Specifies that this 32-bit dword has not been written.
Contains the user data value. This field is initialized to all 1s and can
only be written once.
User data initialized to 1.
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
R/W
R/W
24
1
8
1
DATA
R/W
R/W
23
1
7
1
R/W
R/W
22
1
6
1
R/W
R/W
21
1
5
1
R/W
R/W
20
1
4
1
R/W
R/W
19
1
3
1
INIT1
R/W
R/W
18
1
2
1
June 04, 2007
DBG1
R/W
R/W
17
1
1
1
DBG0
R/W
R/W
16
1
0
0