UPSD3254 STMICROELECTRONICS [STMicroelectronics], UPSD3254 Datasheet - Page 122

• Manufacturer Part Number: UPSD3254
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate External Chip Select
(ECS1-ECS2), routed to Port D.
Although External Chip Select (ECS1-ECS2) can
be produced by any Output Macrocell (OMC),
these External Chip Select (ECS1-ECS2) on Port
D do not consume any Output Macrocells (OMC).
As shown in Figure 58, the CPLD has the following
blocks:
Figure 60. Macrocell and I/O Port
122/175
20 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Macrocell Allocator
Product Term Allocator
PRODUCT TERMS
MACROCELLS
FROM OTHER
PRODUCT TERM
PT
CLOCK
PT CLEAR
CLOCK
SELECT
GLOBAL
CLOCK
ALLOCATOR
PRODUCT TERMS
PT INPUT LATCH GATE/CLOCK
CPLD MACROCELLS
UP TO 10
POLARITY
SELECT
MACROCELL FEEDBACK
PT OUTPUT ENABLE ( OE )
I/O PORT INPUT
PT PRESET
PR DI LD
D/T
CK
D/T/JK FF
SELECT
MCU DATA IN
CL
Q
MCU LOAD
MCU ADDRESS / DATA BUS
SELECT
COMB.
/REG
MACROCELL
CONTROL
OUT TO
DATA
LOAD
MACROCELL
MCU
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD MODULE inter-
nal data bus and can be directly accessed by the
MCU. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
I/O PORT
ALLOC.
TO
AND Array capable of generating up to 137
product terms
Four I/O Ports.
OUTPUT
CPLD
DATA
CPLD OUTPUT
ADDRESS OUT
ALE
I/O PORTS
WR
WR
INPUT MACROCELLS
LATCHED
PDR
D
TO OTHER I/O PORTS
D
REG.
DIR
INPUT
Q
Q
MUX
SELECT
Q
Q D
D
G
AI06602
I/O PIN