UPSD3254 STMICROELECTRONICS [STMicroelectronics], UPSD3254 Datasheet - Page 40

• Manufacturer Part Number: UPSD3254
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
INTERRUPT SYSTEM
There are interrupt requests from 10 sources as
follows.
External Int0
Timer 0 and 1 Interrupts
Timer 2 Interrupt
40/175
INT0 external interrupt
2nd USART interrupt
Timer 0 interrupt
I
INT1 external interrupt (or ADC interrupt)
DDC interrupt
Timer 1 interrupt
USB interrupt
USART interrupt
Timer 2 interrupt
The INT0 can be either level-active or transition-
active depending on Bit IT0 in register TCON.
The flag that actually generates this interrupt is
Bit IE0 in TCON.
When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
If the interrupt was level activated then the
interrupt request flag remains set until the
requested interrupt is actually generated. Then
it has to deactivate the request before the
interrupt service routine is completed, or else
another interrupt will be generated.
Timer 0 and Timer 1 Interrupts are generated by
TF0 and TF1 which are set by an overflow of
their respective Timer/Counter registers (except
for Timer 0 in Mode 3).
These flags are cleared by the internal
hardware when the interrupt is serviced.
Timer 2 Interrupt is generated by TF2 which is
set by an overflow of Timer 2. This flag has to be
cleared by the software - not by hardware.
It is also generated by the T2EX signal (Timer 2
External Interrupt P1.1) which is controlled by
EXEN2 and EXF2 Bits in the T2CON register.
2
C interrupt
I
External Int1
DDC Interrupt
USB Interrupt
2
C Interrupt
The interrupt of the I
in the register S2STA.
This flag is cleared by hardware.
The INT1 can be either level active or transition
active depending on Bit IT1 in register TCON.
The flag that actually generates this interrupt is
Bit IE1 in TCON.
When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
If the interrupt was level activated then the
interrupt request flag remains set until the
requested interrupt is actually generated. Then
it has to deactivate the request before the
interrupt service routine is completed, or else
another interrupt will be generated.
The ADC can take over the External INT1 to
generate an interrupt on conversion being
completed
The DDC interrupt is generated either by Bit
INTR in the S1STA register for DC2B protocol
or by Bit DDC interrupt in the DDCCON register
for DDC1 protocol or by Bit SWHINT Bit in the
DDCCON register when DDC protocol is
changed from DDC1 to DDC2.
Flags except the INTR have to be cleared by the
software. INTR flag is cleared by hardware.
The USB interrupt is generated when endpoint0
has transmitted a packet or received a packet,
when endpoint1 or endpoint2 has transmitted a
packet, when the suspend or resume state is
detected and every EOP received.
When the USB interrupt is generated, the
corresponding request flag must be cleared by
software. The interrupt service routine will have
to check the various USB registers to determine
the source and clear the corresponding flag.
Please see the dedicated interrupt control
registers for the USB peripheral for more
information.
2
C is generated by Bit INTR