UPSD3254 STMICROELECTRONICS [STMicroelectronics], UPSD3254 Datasheet - Page 80

• Manufacturer Part Number: UPSD3254
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Serial Status Register (SxSTA: S1STA, S2STA)
SxSTA is a “Read-only” register. The contents of
this register may be used as a vector to a service
routine. This optimized the response time of the
software and consequently that of the I
The status codes for all possible modes of the I
bus interface are given Table 54.
This flag is set, and an interrupt is generated, after
any of the following events occur.
1. Own slave address has been received during
2. The general call address has been received
Table 53. Serial Status Register (SxSTA)
Table 54. Description of the SxSTA Bits
Note: 1. Interrupt Flag Bit (INTR, SxSTA Bit 5) is cleared by Hardware as reading SxSTA register.
Table 55. Data Shift Register (SxDAT: S1DAT, S2DAT)
80/175
AA = 1: ack_int
while GC(SxADR.0) = 1 and AA = 1:
SxDAT7
GC
2. I
Bit
7
7
6
5
4
3
2
1
0
7
2
C interrupt flag (INTR) can occur in below case. (except DDC2B Mode at SWENB=0)
/ACK_REP
TX_MODE
INTR
SxDAT6
Symbol
BBUSY
BLOST
STOP
STOP
SLV
GC
6
6
(1,2)
General Call Flag
Stop Flag. This bit is set when a STOP condition is received
Interrupt Flag. This bit is set when an I²C Interrupt condition is requested
Transmission Mode Flag.
This bit is set when the I²C is a transmitter; otherwise this bit is reset
Bus Busy Flag.
This bit is set when the bus is being used by another master; otherwise, this bit is reset
Bus Lost Flag.
This bit is set when the master loses the bus contention; otherwise this bit is reset
Acknowledge Response Flag.
This bit is set when the receiver transmits the not acknowledge signal
This bit is reset when the receiver transmits the acknowledge signal
Slave Mode Flag.
This bit is set when the I²C plays role in the Slave Mode; otherwise this bit is reset
SxDAT5
INTR
5
5
TX_MODE
SxDAT4
2
C-bus.
4
4
2
C-
3. A data byte has been received or transmitted in
4. A data byte has been received or transmitted as
5. A stop condition is received as selected slave
Data Shift Register (SxDAT: S1DAT, S2DAT)
SxDAT contains the serial data to be transmitted
or data which has just been received. The MSB
(Bit 7) is transmitted or received first; that is, data
shifted from right to left.
SxDAT3
BBUSY
Master Mode (even if arbitration is lost): ack_int
selected slave: ack_int
receiver or transmitter: stop_int
3
3
Function
SxDAT2
BLOST
2
2
/ACK_REP
SxDAT1
1
1
SxDAT0
SLV
0
0