UPSD3254 STMICROELECTRONICS [STMicroelectronics], UPSD3254 Datasheet - Page 78

• Manufacturer Part Number: UPSD3254
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
I
There are two serial I
uPSD325X devices.
The serial port supports the twin line I
sists of a data line (SDAx) and a clock line (SCLx).
Depending on the configuration, the SDA and SCL
lines may require pull-up resistors.
In both I
I/O port lines as follows.
The system is unique because data transport,
clock generation, address recognition and bus
control arbitration are all controlled by hardware.
Figure 39. Block Diagram of the I
78/175
2
C INTERFACE
SDA1, SCL1: the serial port line for DDC
Protocol
SDA2, SCL2: the serial port line for general I
bus connection
SDA1 / P4.0, SCL1 / P4.1, SDA2 / P3.6, SCL2 /
P3.7
2
C interfaces, these lines also function as
SCLx
SDAx
2
C ports implemented in the
Arbitration and Sync. Logic
2
C Bus Serial I/O
2
C-bus, con-
7
7
7
7
2
C
Bus Clock Generator
Control Register
Status Register
Slave Address
Shift Register
The I
handling and operates in 4 modes.
These functions are controlled by the SFRs.
Master transmitter
Master receiver
Slave transmitter
Slave receiver
SxCON: the control of byte handling and the
operation of 4 mode.
SxSTA: the contents of its register may also be
used as a vector to various service routines.
SxDAT: data shift register.
SxADR: slave address register. Slave address
recognition is performed by On-Chip H/W.
2
C serial I/O has complete autonomy in byte
0
0
0
0
AI06649