UPSD3254 STMICROELECTRONICS [STMicroelectronics], UPSD3254 Datasheet - Page 157

• Manufacturer Part Number: UPSD3254
• Description: Flash Programmable System Devices with 8032 Microcontroller Core
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 79. Synchronous Clock Mode Timing – PLD
Table 122. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
f
t
t
t
t
t
t
t
Symbol
MAX
S
H
CH
CL
CO
ARD
MIN
2. CLKIN (PD1) t
Maximum Frequency
External Feedback
Maximum Frequency
Internal Feedback (f
Maximum Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
CPLD Array Delay
Minimum Clock Period
CLCL
REGISTERED
Parameter
= t
OUTPUT
CLKIN
CH
INPUT
+ t
CNT
CL
.
(2)
)
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
Any macrocell
1/(t
t CH
Conditions
Clock Input
Clock Input
Clock Input
1/(t
1/(t
t
S
CH
+t
CH
S
+t
+t
CO
+t
CL
CO
–10)
CL
)
)
t CL
Min
12
12
0
6
6
t S
t H
t CO
Max
40.0
66.6
83.3
13
11
Aloc
+ 2
+ 2
PT
AI02860
Turbo
+ 10
Off
rate
Slew
– 2
(1)
157/175
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns