ISPPAC-POWR60401TE LATTICE [Lattice Semiconductor], ISPPAC-POWR60401TE Datasheet - Page 12

• Manufacturer Part Number: ISPPAC-POWR60401TE
• Description: In-System Programmable Power Supply Sequencing Controller and Monitor
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
to control the functional states of the sequencer state machine or other control or monitoring logic. The PLD AND
array shown in Figure 2-4 has 20 inputs and 41 product terms (PTs). The resources from the AND array feed the
eight macrocells. The resources within the macrocells share routing and contain a product-term allocation array.
The product term allocation array greatly expands the PLD’s ability to implement complex logical functions by
allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode
functions.
The basic macrocell has five product terms that feed the OR gate and the flip-flop. The flip-flop in each macrocell is
independently configured. It can be programmed to function as a D-Type or T-Type flip-flop. The combinatorial func-
tions are achieved through the bypass MUX function shown. By having the polarity control XOR, the logic reduction
can be best fit to minimize the number of product terms. The flip-flop’s clock drives from a common clock that can
be generated from a pre-scaled, on-board clock source or from an external clock. The macrocell also supports
asynchronous reset and preset functions, derived from product terms, the global reset input, or the power-on reset
signal.
Figure 2-3. ispPAC-POWR604 Macrocell Block Diagram
PT4
PT3
PT2
PT1
PT0
Clock
Polarity
Block Init Product-Term
Global Polarity Fuse for
Init Product-Term
Product-Term Allocation
Global Reset
2-12
Power On Reset
ispPAC-POWR604 Data Sheet
Macrocell Flip-Flop provides
D,T or Combinatorial
Output with Polarity
D/T
R
CLK
P
Q
To ORP