ISPPAC-POWR60401TE LATTICE [Lattice Semiconductor], ISPPAC-POWR60401TE Datasheet - Page 4

• Manufacturer Part Number: ISPPAC-POWR60401TE
• Description: In-System Programmable Power Supply Sequencing Controller and Monitor
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses above those listed values may cause permanent
damage to the device. Functional operation of the device at these or any other conditions above those indicated in
the operating sections of this specification is not implied.
Pin Descriptions (Continued)
VDD
VDD
V
VMON
V
T
T
T
1. V
2. Digital inputs are tolerant up to 5.5V, independent of the V
1. IN1...IN4 are digital inputs to the PLD. The thresholds for these pins are referenced by the voltage on VDDINP.
2. The open-drain outputs can be powered independently of VDD and pulled up as high as +6.0V (referenced to ground). Exception, CLK pin
3. VDDINP can be chosen independent of V
4. The six VMON inputs can be biased independently of VDD. The six VMON inputs can be as high as 7.0V Max (referenced to ground).
5. CLK is the PLD clock output in master mode. It is re-routed as an input in slave mode. The clock mode is set in software during design time.
6. RESET is an active low INPUT pin, external pull-up resistor required. When driven low it resets all internal PLD flip-flops to zero, and may
7. The CREF pin requires a 0.1µF capacitor to ground, near the device pin. This reference is used internally by the device. No additional
8. The four digital outputs (pins 12-15) are named OUT5-OUT8 to match ispPAC-POWR1208 pin names and to allow easy design migration.
Number
A
S
SOL
IN
TRI
Symbol
26 can only be pulled as high as VDD.
In output mode it is an open-drain type pin and requires an external pull-up resistor (pullup voltage must be ≤ V
POWR604 devices can be tied together with one acting as the master, the master can use the internal clock and the slave can be clocked
by the master. The slave needs to be set up using the clock as an input.
turn “ON” or “OFF” the output pins, depending on the polarity configuration of the outputs in the PLD. If a reset function is needed for the
other devices on the board, the PLD inputs and outputs can be used to generate these signals. The RESET connected to the POR pin can
be used if multiple ispPAC-POWR604 devices are cascaded together in expansion mode or if a manual reset button is needed to reset the
PLD logic to the initial state. While using the ispPAC-POWR604 in hot-swap applications it is recommended that either the RESET pin be
connected to the POR pin, or connect a capacitor to ground (such that the time constant is 10 ms with the pull-up resistor) from the RESET
pin.
external circuitry should be connected to this pin.
supply voltage for the given input logic range.
2
DDINP
42
43
44
INP
1
is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V
NC
NC
NC
Core supply voltage at pin
Digital input supply voltage for IN1-IN4
Input voltage applied, digital inputs
Input voltage applied, V
Tristated or open drain output, external voltage applied
(CLK pin 26 pull-up ≤ VDD).
Storage temperature
Ambient temperature with power applied
Maximum soldering temperature (10 sec. at 1/16 in.)
Name
—
—
—
Pin Type
MON
Parameter
DD.
voltage monitor inputs
It applies only to the four logic inputs IN1-IN4.
—
—
—
DDINP
Voltage Range
voltage.
2-4
No Connect
No Connect
No Connect
Conditions
—
—
—
—
—
—
—
—
ispPAC-POWR604 Data Sheet
Description
Min.
-0.5
-0.5
-0.5
-0.5
-0.5
-65
-55
—
DD
DDINP
). Multiple ispPAC-
Max.
pin with appropriate
150
125
260
6.0
6.0
6.0
7.0
6.0
Units
°C
°C
°C
V
V
V
V
V