ISPPAC-POWR60401TE LATTICE [Lattice Semiconductor], ISPPAC-POWR60401TE Datasheet - Page 18

• Manufacturer Part Number: ISPPAC-POWR60401TE
• Description: In-System Programmable Power Supply Sequencing Controller and Monitor
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a “blind” interrogation of any device in
a compliant IEEE 1149.1 serial chain.
Figure 2-8. TAP States
From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the
Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift
state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via
Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction
Register while an external operation is performed. From the Pause state, shifting can resume by re-entering the
Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states.
If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test
mode (steady state = test). This is when the device is actually programmed, erased or verified. All other instructions
are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec-
tively). The ispPAC-POWR604 contains the required minimum instruction set as well as one from the optional
instruction set. In addition, there are several proprietary instructions that allow the device to be configured, verified,
and monitored. For ispPAC-POWR604, the instruction word length is 6-bits. All ispPAC-POWR604 instructions
available to users are shown in Table 2-4.
0
1
Test-Logic-Reset
Note: The value shown adjacent to each state transition represents the signal present
at TMS at the time of a rising edge at TCK.
Run-Test/Idle
0
1
1
0
1
Select-DR-Scan
Capture-DR
Update-DR
Pause-DR
Exit2-DR
Exit1-DR
Shift-DR
0
0
0
1
1
1
2-18
0
1
0
0
1
0
1
Select-IR-Scan
ispPAC-POWR604 Data Sheet
1
Capture-IR
Pause-IR
Update-IR
Exit2-IR
Shift-IR
Exit1-IR
0
0
1
0
1
1
0
1
0
0
1