ISPPAC-POWR60401TE LATTICE [Lattice Semiconductor], ISPPAC-POWR60401TE Datasheet - Page 8

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ISPPAC-POWR60401TE

Manufacturer Part Number
ISPPAC-POWR60401TE
Description
In-System Programmable Power Supply Sequencing Controller and Monitor
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
Lattice Semiconductor
Timing for JTAG Operations
t
t
t
t
t
t
t
t
t
t
t
t
t
1. t
CKMIN
CKH
CKL
MSS
MSH
DIS
DIH
DOZX
DOV
DOXZ
RSTMIN
PWP
PWE
Symbol
PWP
represents programming pulse width for a single row of E
t
t
t
t
CK
MS
DI
DO
Minimum clock period
TCK high time
TCK low time
TMS setup time
TMS hold time
TDI setup time
TDI hold time
TDO float to valid delay
TDO valid delay
TDO valid to float delay
Minimum reset pulse width
Time for a programming operation
Time for an erase operation
t
DOZH
t
t
MSS
DIS
t
t
MSH
DIH
t
CKH
Parameter
t
t
DOV
CKL
t
CKMIN
t
DOXZ
1
2
CMOS cells.
2-8
Conditions
t
t
CK
MS
t
MSS
Program and Erase cycles
executed in Run-Test/Idle
ispPAC-POWR604 Data Sheet
Min
200
200
15
50
15
50
40
40
40
1
t
PWP,
t
PWE
Typ.
t
MSS
Max
200
200
200
100
100
Units
ms
ms
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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