ISPPAC-POWR60401TE LATTICE [Lattice Semiconductor], ISPPAC-POWR60401TE Datasheet - Page 16

• Manufacturer Part Number: ISPPAC-POWR60401TE
• Description: In-System Programmable Power Supply Sequencing Controller and Monitor
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ispPAC-POWR604 Data Sheet
IEEE Standard 1149.1 Interface
In-system programming of the ispPAC-POWR604 is facilitated via an IEEE 1149.1 test access port (TAP). It is used
by the ispPAC-POWR604 as a serial programming interface, boundary scan test is not supported. There are no
boundary scan logic registers in the ispPAC-POWR604 architecture. This does not prevent the ispPAC-POWR604
from functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 compliant devices.
Since the ispPAC-POWR604 is used to powerup other devices, it should be programmed in a separate chain from
PLDs, FPGAs or other JTAG devices.
A brief description of the ispPAC-POWR604 serial interface follows. For complete details of the reference specifica-
tion, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990
(which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the isp-
PAC-POWR604. The TAP controller is a state machine driven with mode and clock inputs. Instructions are shifted
into an instruction register, which then determines subsequent data input, data output, and related operations.
Device programming is performed by addressing various registers, shifting data in, and then executing the respec-
2
tive program instruction. The programming instructions transfer the data into internal E
CMOS memory. It is these
non-volatile memory cells that determine the configuration of the ispPAC-POWR604. By cycling the TAP controller
through the necessary states, data can also be shifted out of the various registers to verify the current ispPAC-
POWR604 configuration. Instructions exist to access all data registers and perform internal control operations.
For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification.
Other registers are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional
user data registers that are defined by the manufacturer. The two required registers are the bypass and boundary-
scan registers. For ispPAC-POWR604, the bypass register is a 1-bit shift register that provides a short path through
the device when boundary testing or other operations are not being performed. The ispPAC-POWR604, as men-
tioned earlier has no boundary-scan logic and therefore no boundary scan register. All instructions relating to
boundary scan operations place the ispPAC-POWR604 in the BYPASS mode to maintain compliance with the
specification.
The optional identification (IDCODE) register described in IEEE 1149.1 is also included in the ispPAC-POWR604.
Six additional user data registers are included in the TAP of the ispPAC-POWR604 as shown in Figure 2-7. Most of
these additional registers are used to program and verify the analog configuration (CFG) and PLD bits. A status
register is also provided to read the status of the six analog comparators.
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