ISPPAC-POWR60401TE LATTICE [Lattice Semiconductor], ISPPAC-POWR60401TE Datasheet - Page 24

• Manufacturer Part Number: ISPPAC-POWR60401TE
• Description: In-System Programmable Power Supply Sequencing Controller and Monitor
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Software-Based Design Environment
Design Entry Software
All functions within the ispPAC-POWR604 are controlled through a Windows-based software development tool
called PAC-Designer. PAC-Designer has an easy-to-use graphical user interface (Figure 2-14) that allows the user
to set up the ispPAC-POWR604 to perform required functions, such as timed sequences for power supply or moni-
tor trip points for the voltage monitor inputs. The software tool gives the user control over how the device drives the
outputs and the functional configurations for all I/O pins. User-friendly dialog boxes are provided to set and edit all
of the analog features of the ispPAC-POWR604. An extension to the schematic screen is the LogiBuilder design
environment (Figure 2-15) that is used to enter and edit control sequences. Again, user-friendly dialog boxes are
provided in this window to help the designer quickly implement sequences that take advantage of the powerful
built-in PLD. Once the configurations are chosen and the sequence has been described by the utilities, the device
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is ready to program. A standard JTAG interface is used to program the E
CMOS memory. The PAC-Designer soft-
ware supports downloading the device through the PC’s parallel port. The ispPAC-POWR604 can be repro-
®
grammed in-system using the software and an ispDOWNLOAD
Cable assembly to compensate for variations in
supply timing, sequencing or scaling of voltage monitor inputs.
Figure 2-14. PAC-Designer Schematic Screen
The user interface (Figure 2-14) provides access to various internal function blocks within the ispPAC-POWR604
device.
Analog Inputs: Accesses the programmable threshold trip-points for the comparators and pin naming conven-
tions.
Digital Inputs: Digital input naming configurations and digital inputs feed into the internal PLD for the sequence
controller.
Sequence Controller: Incorporates a PLD architecture for designing the state machine to control the order and
functions associated with the user-defined power-up sequence/monitor and control.
Logic Outputs: These pins are configured and assigned in the Logic Output Functional Block. The four digital out-
puts are open-drain and require an external pull-up resistor.
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