ISPPAC-POWR60401TE LATTICE [Lattice Semiconductor], ISPPAC-POWR60401TE Datasheet - Page 2

• Manufacturer Part Number: ISPPAC-POWR60401TE
• Description: In-System Programmable Power Supply Sequencing Controller and Monitor
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Power Supply Sequence Controller and Monitor
The ispPAC-POWR604 device is specifically designed as a fully-programmable power supply sequencing controller
and monitor for managing up to four separate power supplies, as well as monitoring up to six analog inputs or sup-
plies. The ispPAC-POWR604 device contains an internal PLD that is programmable by the user to implement digi-
tal logic functions and control state machines. The internal PLD connects to two programmable timers, special
purpose I/O and the programmable monitoring circuit blocks. The internal PLD and timers can be clocked by either
an internal programmable clock oscillator or an external clock source.
The voltage monitors are arranged as six independent comparators each with 192 programmable trip point set-
tings. Monitoring levels are set around the following standard voltages: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V or 5.0V.
All six voltages can be monitored simultaneously (i.e., continuous-time operation). Other non-standard voltage lev-
els can be accounted for using various scale factors.
For added robustness, the comparators feature a variable hysteresis that scales with the voltage they monitor.
Generally, a larger hysteresis is better. However, as power supply voltages get smaller, that hysteresis increasingly
affects trip-point accuracy. Therefore, the hysteresis is +/-16mV for 5V supplies and scales down to +/-3mV for 1.2V
supplies, or about 0.3% of the trip point.
The programmable logic functions consist of a block of 20 inputs with 41 product terms and eight macrocells. The
architecture supports the sharing of product terms to enhance the overall usability.
The four output pins are open-drain outputs. These outputs can be used to drive enable lines for DC/DC converters
or other control logic associated with power supply control. The four outputs are driven from the macrocells.
Figure 2-1. ispPAC-POWR604 Block Diagram
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
RESET
IN1
IN2
IN3
IN4
Analog
Digital
Inputs
Inputs
5
ispPAC-POWR604
6
20 I/P & 8
Controller
Sequence
2 Timers
Macrocell
Internal
250kHz
6
CPLD
CLKIO
GLB
OSC
2-2
4
Comparator
Outputs
Outputs
Logic
ispPAC-POWR604 Data Sheet
COMP1
COMP2
COMP3
COMP4
COMP5
COMP6
OUT5
OUT6
OUT7
OUT8