TE28F008xxx Intel Corporation, TE28F008xxx Datasheet - Page 14

• Manufacturer Part Number: TE28F008xxx
• Description: (TE28F Series) 3 Volt Advanced Boot Block Flash Memory
• Manufacturer: Intel Corporation

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.1.1
3.1.2
3.1.3
3.1.4
8
Read (Array, Status, or Identifier)
Output Disable
Standby
Reset
Write
Table 3.
Mode
Bus Operations
NOTES:
Read
The flash memory has four read modes available: read array, read identifier, read status and read
query. These modes are accessible independent of the V
command must be issued to the CUI to enter the corresponding mode. Upon initial device power-
up or after exit from reset, the device automatically defaults to read array mode.
CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection
control; when active it enables the flash memory device. OE# is the data output control and it
drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at
V
Output Disable
With OE# at a logic-high level (V
high-impedance state.
Standby
Deselecting the device by bringing CE# to a logic-high level (V
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during program or erase operation, the device continues to consume active power until
the program or erase operation is complete.
Deep Power-Down / Reset
From read mode, RP# at V
impedance state, and turns off all internal circuits. After return from reset, a time t
until the initial read access outputs are valid. A delay (t
reset before a write can be initiated. After this wake-up interval, normal operation is restored. The
CUI resets to read array mode, and the status register is set to 80H. This case is shown in
Figure
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].
2. X must be V
3. See DC Characteristics for V
4. Manufacturer and device codes may also be accessed in read identifier mode (A
5. Refer to
6. To program or erase the lockable blocks, hold WP# at V
7. RP# must be at GND
IH
.
Figure 7
9A.
Table 6
IL
illustrates a read cycle.
, V
IH
for valid D
(1)
for control pins and addresses.
2, 5–7
Note
2–4
2, 7
2
2
0.2 V to meet the maximum deep power-down current specified.
IN
IL
PPLK
during a write operation.
for time t
, V
RP#
V
V
V
V
V
IH
IH
IH
IH
IH
PP1
IL
), the device outputs are disabled. Output pins are placed in a
, V
PLPH
PP2
, V
deselects the memory, places output drivers in a high-
CE#
V
V
V
V
PP3
X
IL
IL
IH
IL
, V
PP4
IH
.
PHWL
voltages.
PP
OE#
V
V
V
X
X
IH
IH
IL
voltage. The appropriate Read Mode
or t
IH
PHEL
) places the device in standby
WE#
V
V
V
) is required after return from
X
X
IH
IH
IL
1
–A
21
High Z
High Z
High Z
DQ
D
= 0). See
D
OUT
IN
0–7
PHQV
is required
3UHOLPLQDU\
Table
DQ
High Z
High Z
High Z
D
D
OUT
8–15
IN
5.