TE28F008xxx Intel Corporation, TE28F008xxx Datasheet - Page 19

• Manufacturer Part Number: TE28F008xxx
• Description: (TE28F Series) 3 Volt Advanced Boot Block Flash Memory
• Manufacturer: Intel Corporation

3.2.5.1
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Table 6. Command Bus Definitions
Suspending and Resuming Erase
When the status register indicates that erasure is complete, check the erase status bit to verify that
the erase operation was successful. If the erase operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase failure. If V
the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,
SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to identify that
V
After an erase operation, clear the status register (50H) before attempting the next operation. Any
CUI instruction can follow after erasure is completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in read array mode after the erase is complete.
Since an erase operation requires on the order of seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in order to read data from or program data to
another block in memory. Once the erase sequence is started, writing the Erase Suspend command
to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase
algorithm. The status register will indicate if/when the erase operation has been suspended.
A Read Array/Program command can now be written to the CUI in order to read data from/
program data to blocks other than the one currently suspended. The Program command can
subsequently be suspended to read yet another array location. The only valid commands while
erase is suspended are Erase Resume, Program, Read Array, Read Status Register, or Read
Identifier. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking
CE# to V
Erase Resume continues the erase sequence when CE# = V
operation, the status register must be read and cleared before the next instruction is issued.
NOTES:
1. Bus operations are defined in
2. Following the Intelligent Identifier command, two read operations access manufacturer and device codes.
3. Either 40H or 10H command is valid although the standard is 40H.
4. When writing commands to the device, the upper data bus [DQ
Read Array
Read Identifier
Read Status Register
Clear Status Register
Program
Block Erase/Confirm
Program/Erase Suspend
Program/Erase Resume
PP
A
minimize current draw.
supply voltage was not within acceptable limits.
0
= 0 for manufacturer code, A
PA: Program Address
IA: Identifier Address
Command
IH
. This reduces active current consumption.
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
PD: Program Data
ID: Identifier Data
Notes
Table
2
3
0
(1,4)
= 1 for device code. A
3.
Oper
Write
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
BA: Block Address
SRD: Status Register Data
Addr
X
X
X
X
X
X
X
X
1
–A
21
= 0.
PP
IL
8
40H /
–DQ
Data
FFH
B0H
D0H
90H
70H
50H
10H
20H
was not within acceptable limits after
. As with the end of a standard erase
15
] should be either V
Read
Read
Oper
Write
Write
Second Bus Cycle
Addr
PA
BA
IA
X
IL
or V
IH
, to
Data
SRD
D0H
PD
ID
13