USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 16

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USB97C201-MN

Manufacturer Part Number
USB97C201-MN
Description
USB 2.0 ATA/ ATAPI Controller
Manufacturer
SMSC [SMSC Corporation]
Datasheet
6.1.3
SMSC DS – USB97C201
MCU BLOCK REGISTER SUMMARY
ADDRESS
C0
9C
9D
9A
9B
9F
A1
A2
A5
A0
A6
80
93
90
94
95
96
97
UTIL_CONFIG
SRAM_DATA
SRAM_ADD1
SRAM_ADD2
CLOCK_SEL
WU_SRC_1
WU_MSK_1
GPIO_OUT
GPIO_MSK
GPIO_DIR
GPIO_IRQ
DEV_REV
GPIO_IN
DEV_ID
NAME
IMR_0
IMR_1
ISR_0
ISR_1
(These registers are external to the 8051 design core)
Table 4 - MCU Block Register Summary
POWER MANAGEMENT REGISTERS
PRELIMINARY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
RUNTIME REGISTERS
UTILITY REGISTERS
INT0 Source Register
INT0 Mask Register
INT1 Source Register
INT1 Mask Register
Device Revision Register
Device ID Register
GPIO Direction Register
GPIO Data Output Register
GPIO Data Input Register
GPIO Interrupt Status Register (INT4)
GPIO Interrupt Mask Register (INT4)
Miscellaneous Configuration Register
SRAM Data Port Register
Wakeup Source 1 Register (INT2)
SRAM Address 1 Register
SRAM Address 2 Register
8051 Clock Select Register
Wakeup Mask 1 Register (INT2)
Page 16
DESCRIPTION
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Rev. 03/25/2002

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