USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 9

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USB97C201-MN

Manufacturer Part Number
USB97C201-MN
Description
USB 2.0 ATA/ ATAPI Controller
Manufacturer
SMSC [SMSC Corporation]
Datasheet
4.0 BLOCK DIAGRAM
SMSC DS – USB97C201
External PHY
OPTIONAL
Auto address generators
( Serial Interface Engine )
( Transceiver )
RAMWR_A/B
USB 2.0 PHY
RAMRD_A/B
EP0TX_BC
EP0RX_BC
EP1TX_BC
EP1RX_BC
SIE
Granted SRAM access
during Phase 0
Address
Address
Address
Address
CLOCKOUT
32 bit 15MHz Data Buss
Configuration and Control
Clock Generation
SIE Control Regs
12 MHz
Osc
Page 9
Address
Latch phase 0
PRELIMINARY
32 Bit
512 Bytes EP2 TX/RX Buffer B
512 Bytes EP2 TX/RX Buffer A
Interrupt Controller
64 Bytes EP1RX
64 Bytes EP1TX
64 Bytes EP0RX
64 Bytes EP0TX
Latch phase 1
CPU CORE
FAST 8051
60MHz
Latch phase 2
Granted SRAM access during Phase 1
Data @ 32 bit
15MHz
1.25KB
SRAM
Rev. 03/25/2002
Future phase 3
Program/Scratchpad
768 Byte
SRAM
GPIO
Interface
ATA-66
MEM/IO Bus
29pins
Granted SRAM access
during Phase 2
8 pins
ATA/ATAPI
Drive
Program Memory/ IO
Bus

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