USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 51

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

Trapezoidal shapes indicate actions performed by the firmware. The hardware state machine is responsible for
automatically changing the state of RAMWR_TOGGLE according to the state change of the RAMWR_B and
RAMWR_A bits, as shown in Table 65 . These bits are normally set by the USB97C201 upon completion of loading
the A or B SRAM buffer and are normally cleared by the firmware (except when Auto Transfer operation is enabled,
see Section 6.9.3).
Note that when both buffers are “full”, ie RAMWR_A and RAMWR_B status bits are BOTH set, that the
RAMWR_TOGGLE is not altered and that flow control is initiated on the input source. If this source is the SIE, it will
NYET or NAK further OUTs. If it is the ATA interface, nDAK will not be asserted in response to DRQ and data not
clocked in to the SRAM.
6.9.2
Figure 4 illustrates the operation of the transmit A and B buffers.
SMSC DS – USB97C201
TRANSMIT BUFFER OPERATION
0
0->1
1
0->1
1->0
1
RAMWR_B
CLR RAMWR_B;
RAMWR_TOGGLE=1;
(IN FLOW CONTROL
OFF)
RAMWR_A
CLEAR
0->1
0
0->1
1
1
1->0
RAMWR_A
Yes
Yes
FIGURE 3 - RECEIVE BUFFER OPERATION
Table 65 – RAMWR_TOGGLE State Control
A Buffer Output
RAMWR_A=1
RAMWR_B=0
Completed?
TOGGLE=1
SRAM Data
Received?
RAMWR_
Yes
No
B
No
PRELIMINARY
B Buffer Output
SRAM Data
Completed?
Received?
Yes
No
A
No
0->1
1->0
No Change (0)
No Change (1)
X->1
X->0
RAMWR_TOGGLE
Yes
Yes
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(IN FLOW CONTROL
RAMWR_A=0
RAMWR_B=0
RAMWR_A=1
RAMWR_B=1
TOGGLE=0?
TOGGLE=0?
RAMWR_
RAMWR_
ACTIVE)
POR
No
No
A Buffer Output
SRAM Data
Completed?
No
Received?
No
B
Yes
A buffer filled; B buffer empty;
change to B buffer buffer
B buffer filled, A buffer empty;
change to A buffer buffer
Both buffers filled; source flow
controlled.
Both buffers filled; source flow
controlled
B buffer emptied; A buffer full;
change to A buffer buffer.
A buffer emptied; B buffer full;
change to A buffer buffer.
B Buffer Output
RAMWR_A=0
RAMWR_B=1
Completed?
TOGGLE=0
SRAM Data
Received?
RAMWR_
Yes
No
A
No
Yes
Yes
COMMENT
RAMWR_B
CLR
(IN FLOW CONTROL OFF)
RAMWR_TOGGLE;
CLR RAMWR_A;
CLR
Rev. 03/25/2002