USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 49

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

6.7 SRAM Time Multiplexer Operation
The SRAM access, read or write, occurs in four sequential phases, Ø0-3. These periods are 16.666ns long (60Mhz)
and are non-overlapping. Data to/from the SRAM are buffered by local DWORD latches close to the SRAM to
minimize high-speed bussing. The rest of the USB97C201 subsystems access these latches during the phases
when they are NOT being used to transfer data to/from the SRAM.
6.7.1
During this phase, the SIE has access to the SRAM through its associated DWORD latches.
If data from EP0 or EP1 is ready (ie either a full DWORD or the end of a packet has been received), this data will be
written into the appropriate buffer address space and the associated EPxRX_BUF register incremented to reflect the
amount of buffer used to this point. If data to EP0 or EP1 is required by the SIE, it will load the data from the SRAM
into the DWORD latch whose address is determined by an incrementing address counter. This counter will be
compared against the EPx_TX register value, to determine if the buffer transfer has been completed.
If the DIR bit in EP2_CTL is “0”, and data is requested by the SIE for transmission to the host on EP2, the TOKEN
error bit in the USB_ERR register will be set and no other action occurs. If data is received by the SIE on EP2 (IN
tokens) and either a full DWORD or EOP has been received, then this data will be written into either the SRAM A or
SRAM B buffer space, as appropriate, and the associated RAMWRBC_ A/B registers incremented.
If the DIR bit in EP2_CTL is “1”, and data is received by the SIE from the host on EP2, the TOKEN error bit in the
USB_ERR register will be set and no other action occurs. If data to EP2 is required by the SIE from the SRAM, the
data will be loaded in the DWORD latch from the A or B buffer space, as appropriate. The SRAM data address will
be determined by an incrementing address counter which will be compared against the RAMRDBC_A/B registers’
value to determine if the buffer transfer has been completed.
6.7.2
The ATA interface block has access to the SRAM via a DWORD latch during this phase.
I
f the DIR bit in EP2_CTL is “1”, when either a full DWORD or end of DMA has been received by the ATA interface
from the ATAPI/ATA device and loaded in to the DWORD latch, it will be written into either the A or B buffer space,
as appropriate, and the associated RAMWRBC_ A/B registers incremented.
If the DIR bit in EP2_CTL is “0”, data will be loaded in the DWORD latch from the A or B buffer space, as
appropriate, when the ATA interface requires data to be sent to the ATAPI/ATA device. The SRAM data address will
be determined by an incrementing address counter, which will be compared against the RAMRDBC_A/B registers’
value to determine if the buffer transfer has been completed.
6.7.3
During this phase, the DWORD latch that interfaces to the SRAM_DATA register will be normally repetitively loaded
with data READ from the SRAM at the address determined by the higher order bits of the SRAM_ADD1/2 register.
The 8051 can read this data with a read to the SRAM_DATA port. Bits 0&1 of the SRAM_ADD1 register will
determine the byte read of the DWORD latch.
In order to write data from the 8051 to the SRAM, the 8051 will write the data into the SRAM_DATA register. The
sub-byte of the DWORD latch determined by bits 0 & 1 of the SRAM_ADD1 register will be updated, and the entire
DWORD will be written to the SRAM at the address determined by the higher order address bits of the
SRAM_ADD1/2 registers during the next Ø2 interval. Subsequently, it will return to reading the SRAM data into the
DWORD latch on each Ø2 interval. This allows single byte modifications of the the 32 bit wide SRAM to be executed
by the 8051.
6.7.4
Phase 3 is an idle period during which no accesses occur to the SRAM. This period is reserved for future expansion
in derivative products to allow another high speed access path for additional IO.
6.8 EP2 SRAM Buffer Operation
In order to illustrate the operation of the buffering and the interactions between the SIE and ATA control blocks and
the firmware, the following scenario will be explained in detail in a timeline format for operation NOT using the Auto
Toggle or Auto Transfer features (ie totally firmware controlled):
1.
SMSC DS – USB97C201
Endpoint 2 is currently receiving data (ie a file segment) from the host for transfer to the ATA interface (DIR bit
of EP2_CTL = 0). The SRAM B buffer assigned to EP2 has just been filled with data from the SIE (ie a max
packet has been received).
PHASE 0 (Ø0)
PHASE 1 (Ø1)
PHASE 2 (Ø2)
PHASE 3 (Ø3)
PRELIMINARY
Page 49
Rev. 03/25/2002