USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 46

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

The first data port read of a sector is called the demand read. Subsequent data port reads from the sector are called
prefetch reads. The demand read and all prefetch reads must be of the same size (16 or 32 bits).
Data posting is performed for writes to the IDE data ports. The IDE CONTROLLER will then run the IDE cycle to
transfer the data to the drive.
6.3.4
When enabled and supported by the device, DMA transfers are executed on the IDE interface, the chip selects
(IDE_nCS1/0) will be negated (high). When the IDE device asserts IDE_DRQ, the IDE Controller will return
IDE_nDACK to the IDE device when it is ready for the DMA data transfer. For multiword DMA transfers, the
IDE_nIOR or IDE_nIOW signal will free run at the programmed rate as long as IDE_DRQ remains asserted and the
IDE Controller is prepared to complete a data transfer. If IDE_DRQ has not de-asserted by the rising edge of
IDE_nIOR or IDE_nIOW signal multiword DMA is assumed and at least one more cycle will be executed. If
IDE_DRQ de-asserts before IDE_nIOR or IDE_nIOW is de-asserted while IDE_nDACK is asserted, it indicates that
one last data transfer remains for the current session. In this case, IDE_nDACK will be de-asserted one clock after
the IDE_nIOR or IDE_nIOW signal de-asserts. This allows the IDE controller to support both single and multiword
DMA cycles automatically.
The IDE device’s DMA request signal is sampled when the IO strobe is deasserted. If inactive, the DMA
Acknowledge signal is deasserted and no more transfers take place until DMA request is again asserted.
The controller transfers data to or from the EP2 buffer(s) responding to the DMA requests from the IDE device. The
controller will continue this until stopped or the byte count in ATA_CNT[3:0] reaches zero.
6.3.4.1
The IDE device signals an interrupt (IDE_IRQ) once its programmed data count has been transferred or an error
occurs. The IDE device will also deassert its DMA request signal, causing the IDE Controller to stop transferring
data. On reads from the IDE device, it will cause any data read from the device to be transferred to the EP2 buffer(s),
as they become available.
6.3.5
Ultra ATA/66 is a new IDE transfer protocol used to transfer data between a Ultra ATA/66 capable IDE controller and
Ultra ATA/66 capable IDE devices. Ultra DMA/66 utilizes a “source synchronous” signaling protocol to transfer data
at rates up to 66 Mbytes/sec.
6.3.5.1
Although no additional signal pins are required for Ultra ATA/66 operation, the operation of some standard IDE
controller pins are redefined during Ultra ATA modes of operation. The Ultra DMA/66 protocol defines three hand-
shaking signals: STOP, STROBE and DMARDY. Table 63 shows the mapping of the redefined Ultra ATA/66 signals
onto the standard IDE controller pins.
STOP: STOP is always driven by the the USB97C201 and is used to request that a transfer be stopped or as an
acknowledgment to stop a request from IDE device. The IDE_nIOW signal is redefined as STOP for both read and
write transfers.
STROBE : This is a data strobe signal driven by the TRANSMITTER of a data transfer, which is either the IDE device
of a DMA Read transfer or the USB97C201 of a DMA Write transfer, on which data is transferred during each rising
and falling edge transition of the signal. The IORDY signal is redefined as STROBE for reads (when transferring data
from the IDE device to the USB97C201). The IDE_nIOR signal is redefined as STROBE for writes (transferring data
from the USB97C201 to the IDE device).
nDMARDY: This is a signal driven by the RECEIVER of a data transfer, which is either the USB97C201 of a DMA
Read transfer or the IDE device of a DMA Write transfer, to signal that the RECEIVER is ready to transfer data or to
add wait states to the current transaction. The IDE_nIOR signal is redefined as nDMARDY for reads (when
transferring data from the IDE device to the USB97C201). The IORDY signal is redefined as nDMARDY for writes
(transferring data from the USB97C201 to the IDE device).
SMSC DS – USB97C201
DMA TRANSFERS
ULTRA ATA/66 SYNCHRONOUS DMA OPERATION
Completion of DMA Data Transfers
Ultra ATA/66 Signals
Table 63 – ULTRA ATA/66 Control Signal Assignments
IDE SIGNAL
STANDARD
PRELIMINARY
DURING ULTRA
SIGNAL NAME
ATA/66 READ
Page 46
DURING ULTRA
SIGNAL NAME
ATA/66 WRITE
Rev. 03/25/2002