USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 18

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

These registers are part of the 8051 design core itself.
Notes:
Note: the strobe width will vary with the actual clock divider used for the processor. For example if, 16 Mhz is used,
an MD[2:0] value of 111 will result in a 28 clock strobe or 1866ns.
SMSC DS – USB97C201
REGISTER
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
SPC_
FNC
EXIF
MPAGE
SCON0
SBUF0
IE
IP
TL2
TH2
PSW
EICON
ACC
EIE
B
EIP
Bits MD2:0 of the CKCON SFR register (8Eh) control the cycle timing for external accesses using the nIOR and
nIOW signals. This allows slow peripheral devices to be attached. The values and corresponding strobe widths
are shown below:
Bit WRS of the SPC_FNC register controls the operation of MOVX writes the program or XDATA bus of the
8051. Setting it to 0 ( the reset state), will direct writes to the XDATA bus, either to internal or external
destinations, while setting it to 1 will allow writes to the program memory bus to occur, either internally( if the
768 SRAM is the target) or externally.
MD2
0
0
0
0
1
1
1
1
BIT7
0
SMOD0
TF1
GATE
0
IE5
SM0_0
EA
1
CY
SMOD1
1
1
MD1
0
0
1
1
0
0
1
1
–
1
BIT6
0
TR1
C/T
0
IE4
SM1_0
ES1
PS1
AC
1
1
MD0
0
1
0
1
0
1
0
1
Table 5 - 8051 Core SFR Register Summary
BIT5
0
1
TF0
M1
T2M
0
IE3
SM2_0
ET2
PT2
F0
EPFI
1
1
PRELIMINARY
NIOR/NIOW STOBE
(CLKS)
BIT4
0
1
TR0
M0
T1M
0
IE2
REN_0
ES0
PS0
RS1
PFI
EWDI
PWDI
12
16
20
24
28
2
4
8
Page 18
BIT3
0
GF1
IE1
GATE
T0M
0
1
TB8_0
ET1
PT1
RS0
WDTI
EX5
PX5
BIT2
0
GF0
IT1
C/T
MD2
0
0
RB8_0
EX1
PX1
OV
0
EX4
PX4
NIOR/NIOW STROBE (AT
BIT1
0
STOP
IE0
M1
MD1
0
0
TI_0
ET0
PT0
F1
0
EX3
PX3
30MHZ)
133ns
267ns
400ns
533ns
667ns
800ns
933ns
66ns
BIT0
SEL
IDLE
IT0
M0
MD0
WR
S
0
RI_0
EX0
PX0
P
0
EX2
PX2
ADDRESS
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
91h
92h
98h
99h
A8h
B8h
CCh
CDh
D0h
D8h
E0h
E8h
F0h
F8h
Rev. 03/25/2002