USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 40

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

SMSC DS – USB97C201
Cycle Time)
Mode (Data
Bit Settings
[7:3]
[2:0]
BIT
Strobe
[7:6]
[5:4]
BIT
3
(0xDF - RESET=0x00)
(0xDE - RESET=0x00)
DMA_TMG[2:0]
Reserved
NAME
IDE_TIM
ATA_DMA
ISP[1:0]
(~1267ns)
RT[0:1]
NAME
Mode 0
DTE
000
Table 58 –ATA Ultra DMA Timing Register
R/W
R/W
R/W
R/W
R/W
R/W
R
Table 59 – IDE Timing Register
PRELIMINARY
ULTRA DMA TIMING MODES
(~167ns)
Mode 1
001
IORDY Sample Point. This field selects the number of 30MHz
clocks (33ns/clock) between IDE_nIOx assertion and the first
IORDY sample point. In fast PIO timing mode (See bit 3
below), this sets the active period for the data strobe.
Bits [7-6]Number of Clocks
00
01
10
11
Recovery Time. This field selects the minimum number of
30MHz clocks(33ns/clock) between the last IORDY sample
point and the next IDE_nIOx strobe. In fast PIO timing mode
(See bit 3 below), this sets the inactive period for the data
strobe.
Bits [5-4]Number of Clocks
00
01
10
11
DMA Timing Enable Only.
1: Fast timing mode is enabled for non-UDMA DMA data. PIO
transfer to the IDE data port will run in compatible timing.
0: Both non-UDMA DMA and PIO data transfers to drive will
use the fast timing mode.
These bits always reads “0”.
Drive Timing.
These bit settings the Ultra DMA mode that the ATA
interface operates when Ultra DMA operation is enabled.
They therefore determine the minimum data write strobe
Cycle Time (CT) and minimum Ready to Pause time (RP).
are shown below:
000: CT= 267ns, RP= 333ns (Mode 0)
001: CT= 167ns, RP= 266ns (Mode 1)
010: CT= 133ns, RP= 200ns (Mode 2)
011: CT= 100ns, RP= 200ns (Mode 3)
100: CT= 66ns, RP= 200ns (Mode 4)
101 thru 111 reserved
Page 40
5 clocks
4 clocks
3 clocks
2 clocks.
4 clocks
3 clocks
2 clocks
1 clock.
ATA ULTRA DMA TIMING REGISTER
(~133ns)
Mode 2
010
IDE TIMING REGISTER
DESCRIPTION
DESCRIPTION
(~100ns)
Mode 3
011
(~66ns)
Mode 4
100
Rev. 03/25/2002