USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 35

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

Note: A zero length packet may be sent by just clearing this register and setting the TX bit in the EP0TX_CTL
register.
Notes:
Note: A zero length packet may be sent by just clearing this register and setting the TX bit in the EP1TX_CTL
register.
SMSC DS – USB97C201
This register is updated at the end of a transfer and is actually the least significant bits of the ending address in
the SRAM buffer.
This register is cleared if a SETUP packet is received on EP0.
[5:0]
[5:0]
[5:0]
[7:2]
BIT
BIT
BIT
BIT
[7:0]
BIT
7
6
7
6
7
6
1
0
(0xCE - RESET=0x00)
(0xB6 - RESET=0x00)
(0xB7 - RESET=0x00)
(0xC7 - RESET=0x00)
(0xD1 - RESET=0x00)
(0xCF- RESET=0x00)
COUNT[7:0]
Reserved
Reserved
Reserved
RAMWRBC_A1
Reserved
RAMWRBC_A2
RAMWRBC_B1
512Bytes
COUNT8
64BYTE
64BYTE
64BYTE
COUNT
COUNT
COUNT
NAME
NAME
NAME
NAME
EP1RX_BC
NAME
EP0TX_BC
EP1TX_BC
Table 41 – RAM BUFFER WRITE Byte Count Register A2 Register
Table 40 – RAM Buffer Write Byte Count Register A1
Table 42 – RAM Buffer Write Byte Count Register B1
Table 37 – Endpoint 0 Transmit Byte Count Register
Table 39 – Endpoint 1 Transmit Byte Count Register
Table 38 – Endpoint 1 Receive Byte Count Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
PRELIMINARY
This bit always reads “0”.
1 = Indicates that 64 Bytes are to be transmitted.
Indicates the byte count of the packet to be sent on EP0
and stored in SRAM beginning at address 0x0040.
This bit always reads “0”.
1 = Indicates that 64 Bytes were received.
Indicates the byte count of the packet received on EP1 and
stored in SRAM beginning at address 0x0080.
This bit always reads “0”.
1 = Indicates that 64 Bytes are to be transmitted.
Indicates the byte count of the packet to be sent on EP1
and stored in SRAM beginning at address 0x00C0.
This bit always reads “0”.
1 = Indicates that 512 bytes were transferred
Bit 8 of the byte count for the data transferred.
Bits 7 thru 0 the byte count of the data transferred to the
SRAM. The data is stored beginning at address 0x0100
RAM BUFFER WRITE BYTE COUNT REGISTER A1
RAM BUFFER WRITE BYTE COUNT REGISTER A2
RAM BUFFER WRITE BYTE COUNT REGISTER B1
ENDPOINT 0 TRANSMIT BYTE COUNT REGISTER
ENDPOINT 1 TRANSMIT BYTE COUNT REGISTER
ENDPOINT 1 RECEIVE BYTE COUNT REGISTER
Page 35
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
Rev. 03/25/2002