HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet
HI-6120
Available stocks
Related parts for HI-6120
HI-6120 Summary of contents
Page 1
... MIL-STD-1553 Remote Terminal in a monolithic sili- con gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus inter- face for access to registers and RAM and is offered in a 100-pin plastic quad flat pack (PQFP). The HI-6121 has ...
Page 2
... NOTES: HI-6120, HI-6121 HOLT INTEGRATED CIRCUITS 2 ...
Page 3
... Pending Interrupt Register (0x0006) ........................................................................ 31 5.8. 1553 Status Word Bits Register (0x0007) ................................................................ 33 5.9. Time-Tag Register (0x0008) ..................................................................................... 34 5.10. Interrupt Log Address Register (0x0009).................................................................. 35 5.11. Current Message Information Word Address Register (0x000A) ............................. 35 5.12. Memory Address Pointer Register (HI-6121 only) (0x000F) ................................... 36 5.13. Interrupt Enable Register (0x0010) .......................................................................... 36 HI-6120, HI-6121 HOLT INTEGRATED CIRCUITS 3 ...
Page 4
... Transmit Subaddress Command ............................................................................... 72 11.2. Mode Command Message Information Words ........................................................... 73 11.2.1. Receive Mode Command ........................................................................................... 73 11.2.2. Transmit Mode Command .......................................................................................... 75 11.3. Ping-Pong Data Buffering ........................................................................................... 78 11.3.1. Double Buffered (Ping-Pong) Mode ............................................................................ 78 11.3.2. Ping-Pong Enable / Disable Handshake ..................................................................... 78 11.3.3. Broadcast Message Handling in Ping-Pong Mode ..................................................... 80 11.4. Indexed Data Buffer Mode .......................................................................................... 82 11.4.1. Single Message Mode................................................................................................. 82 HI-6120, HI-6121 HOLT INTEGRATED CIRCUITS 4 ...
Page 5
... Software Reset ......................................................................................................... 105 14.3. Reset Remote Terminal Mode Code ........................................................................ 105 14.4. Serial EEPROM Programming Utility ...................................................................... 105 15. HOST INTERFACE ........................................................................................ 107 15.1. HI-6120 Host Bus Interface ...................................................................................... 107 15.1.1. Bus Wait States and Data Prefetch ........................................................................... 107 15.2. HI-6121 Serial Peripheral Interface .......................................................................... 108 15.2.1. Serial Peripheral Interface (SPI) Basics ................................................................... 108 15.2.2. HI-6121 SPI Commands ........................................................................................... 109 15 ...
Page 6
... Absolute Maximum Ratings ...................................................................................... 144 17.2. Recommended Operating Conditions ...................................................................... 144 17.3. DC Electrical Characteristics .................................................................................... 144 17.4. AC Electrical Characteristics ― HI-6121 Host Bus Interface Timing........................ 145 17.5. AC Electrical Characteristics ― HI-6120 Host Bus Interface Timing........................ 146 18. MIL-STD-1553 BUS INTERFACE .................................................................. 151 19. THERMAL CHARACTERISTICS ................................................................... 152 20. ADDITIONAL PIN / PACKAGE CONFIGURATIONS ..................................... 152 20 ...
Page 7
... Figure 1. HI-6120 / HI-6121 Block Diagram................................................................................. 10 Figure 2. Address Mapping for Registers and RAM .................................................................... 19 Figure 3. MIL-STD-1553 Command Word Structure ................................................................... 46 Figure 4. Deriving the Illegalization Table Address From the Received Command Word ........... 49 Figure 5. Fixed Address Mapping for Illegalization Table ........................................................... 50 Figure 6. Summary of Illegalization Table Addresses for Mode Code Commands ...................... 51 Figure 7 ...
Page 8
... Figure 26. MIL-STD-1553 Direct Coupled Test Circuits ............................................................. 151 Figure 27. MIL-STD-1553 Transformer Coupled Test Circuits ................................................... 151 HI-6120, HI-6121 HOLT INTEGRATED CIRCUITS 8 ...
Page 9
... Table 1. Pin Descriptions (Both HI-6120 and HI-6121) .................................................................11 Table 2. Pin Descriptions (HI-6120 only) ..................................................................................... 14 Table 3. Pin Descriptions (HI-6121 only) ..................................................................................... 15 Table 4. Register Summary ......................................................................................................... 20 Table 5. Settings and Responses to Interrupt-Causing Messages .............................................. 38 Table 6. Interrupt Information Word Bits Summary ...................................................................... 52 Table 7. Summary of Data Buffer Modes. ................................................................................... 70 Table 8. Circular Buffer Mode 2 (Initialization factors based on message block size) ................. 91 Table 9 ...
Page 10
... ACKHW ACKMES SSYSF MR INTHW DISCRETE SIGNAL INTMES INTERFACE READY TO HOST ACTIVE * Combined into ACKINT pin on HI-6121PQx variant Figure 1. HI-6120 / HI-6121 Block Diagram HI-6120, HI-6121 SHARED STATIC RAM AND REGISTERS 32K X 16 ADDRESS SPACE CONTROL MEMORY ADDRESS ACCESS MANAGER DATA REMOTE SEQUENCER ...
Page 11
... PIN DESCRIPTIONS Table 1. Pin Descriptions (Both HI-6120 and HI-6121) Pin Function Description Hardware Interrupt output, active low.This signal is programmed as a brief low- INTHW OUTPUT going pulse output level output by the INTSEL bit in Configuration Regis- ter 1. Message Interrupt output, active low. This signal is programmed as a brief low-go- ...
Page 12
... Subsystem fail input, active high. Internal 50KΩ pull-down resistor. When this SSYSF INPUT input is high, the HI-6120 / HI-6121 terminal sets the SUBSYS flag in its status word. Chip select output for the dedicated Serial Peripheral Interface (SPI) that con- nects to the optional external serial EEPROM used for automatic self-initialization. ...
Page 13
... BWID equals 0. BENDI INPUT When the HI-6120 is configured for 16-bit bus width, the BENDI input pin is “don’t care.” When using the HI-6121, this pin controls the byte order of the 16-bit data following the SPI command. ...
Page 14
... Configuration pin for WAIT output polarity. Internal 50KΩ pull-up resistor. When WPOL is low, the “wait” output is active low (WAIT). When WPOL is high, the “wait” output is active high (WAIT). The HI-6120 uses pre-fetching to speed up WPOL INPUT any series of reads from successive addresses. As long as successive reads are sequential, only the first word’ ...
Page 15
... After interrupt assertion causes the INTHW or INTMES output (HI-6121PQX INPUT to go low, a high state (60ns minimum duration) on ACKINT will clear the INTHW variant only) or INTMES output to logic 1. Interrupt outputs on INTHW and INTMES are also cleared by reading the Pending Interrupt Register. HI-6120, HI-6121 HOLT INTEGRATED CIRCUITS 15 ...
Page 16
... FUNCTIONAL OVERVIEW The Holt HI-6120 or HI-6121 provides a complete Re- mote Terminal (RT) interface between a host and a MIL-STD-1553B dual redundant data bus. It automati- cally handles all aspects of the MIL-STD-1553 protocol, namely, encoding/decoding, message formatting, error checking, message data buffering, protocol checking, illegalization and default terminal responses. Internal ...
Page 17
... A free-running 16-bit counter provides time-tag values that are recorded for each message transacted. The time-tag counter can be clocked from one of six inter- HI-6120, HI-6121 nally generated frequencies, or from an external source. The user can enable automatic counter synchronization in response to “synchronize” mode commands, and op- ...
Page 18
... To provide byte capability, the HI-6120 has a sixteenth bus address input, A0. Byte oriented address- ing with the HI-6120 uses all 16 address pins, A15:A0 to address 64K bytes. The A0 input denotes whether the first or second byte in the word is being addressed, while HI-6120, HI-6121 A15:A1 indicate the word address ...
Page 19
... Illegalization Table. Initialized by the host, this table identifies illegal commands. 256 Words 0x0100 0x00FF Expanded at right 0x0000 Figure 2. Address Mapping for Registers and RAM HI-6120, HI-6121 0x00FF 0x0060 0x005F 0x0040 0x003F 0x0020 0x001F 0x0000 HOLT INTEGRATED CIRCUITS 19 Unallocated Memory. ...
Page 20
... REGISTERS Residing at the start of the memory address space, 32 addresses are reserved for HI-6120 and HI-6121 registers. Register addresses overlay the shared RAM address space, but are separate from the shared dual-port RAM. All register bits are active high. Unless otherwise indicated, all registers are reset in software to the logic zero condition after Master Reset (except any bits reflecting the state of input pins) ...
Page 21
... NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un- changed unless specifically indicated by an “SR” value. Bit No. Mnemonic R/W Reset 15 INHBUSA R/W 14 INHBUSB R/W 13 INTSEL R/W HI-6120, HI-6121 LSB Function Bus A Inhibit. ...
Page 22
... R/W ( HI-6120, HI-6121 Function Shutdown Select. This bit affects terminal response to “transmitter shutdown” mode code commands and only applies when the MCOPT4 bit in Configuration Register 2 equals logic 0 for automatic shutdown after “transmitter shut- down” and “selected transmitter shutdown” mode code commands. When MCOPT4 and SDSEL are both logic 0, a valid “ ...
Page 23
... Single-Strobe Read for 8-Bit Parallel Bus Mode. This bit only applies to HI-6120 (not HI-6121) and only applies when the parallel host bus is configured for 8-bit bus width. When performing 2-byte read accesses of external memory, some microprocessors with 8-bit bus assert individual Read Enable (or STROBE) pulses for high and low bytes ...
Page 24
... NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset. Bit No. Mnemonic R/W Reset Function 15,14 TOSEL1:0 R TRXDB R TTLOAD R/W 0 HI-6120, HI-6121 LSB Time-Out Select for RT-RT Receive Commands. These bits select the “no response” time-out for RT-RT receive commands. ...
Page 25
... R MCOPT4 R/W 0 HI-6120, HI-6121 Reset Time-Tag Counter. Assertion of this bit clears the Time-Tag counter and counting is disabled until the bit is negated. Also the “synchronize” mode command (MC1) causes automatic Time-Tag counter reset. Alternate BIT Word Enable. If this bit is logic 0, the device responds to a “transmit BIT word” mode com- mand (MC19) by sending the word stored in the Built-In Test Word register, at address 0x0014 ...
Page 26
... MCOPT4 R/W 0 (continued) HI-6120, HI-6121 The “selected transmitter shutdown” (MC20 decimal) and “override selected transmitter shutdown” (MC21 decimal) mode commands act similarly to MC4 and MC5 respectively, except bus shutdown (or shutdown override) is condi- tional, based on the value of a mode data word received with the command. ...
Page 27
... MCOPT1 R MCOPT0 R/W 0 4-0 ----- R/W 0 HI-6120, HI-6121 The MCOPT4 bit in Configuration Register 2 is logic 1 MC20 (or MC21) Inactive Bus Tx & mode data status NOT changed value matches (Host can modify “Bus Select” BUSINH bit in Con- value figuration Reg 1) MC20 (or MC21) if mode data Inactive Bus Tx & ...
Page 28
... RTAP R/W PIN 9 LOCK R/W PIN 8 AUTOEN R PIN 7 READY R HI-6120, HI-6121 LSB Function Remote Terminal Address bits Remote Terminal Address Parity. These bits contain the active remote terminal address. After a rising edge on the MR master reset input signal, these bits reflect the state of the RTA4 - 0 and RTAP input pins ...
Page 29
... RAMIF R 0 HI-6120, HI-6121 Function Active status. When set, this read-only bit indicates the terminal is presently processing a message. This bit reflects the state of output pin ACTIVE and is cleared on reset. Note: Ths bit and the corresponding output pin are asserted upon valid command detection and negated when command processing is com- pleted ...
Page 30
... Descriptor Table. For fast context switching, the host may initialize multiple Descriptor Tables, then update this register to load the new base address when the active Descriptor Table changes. The base address must be chosen with bits 7:0 = 00000000. These bits (and the highest address bit) cannot be set in the register. The primary Descriptor Table HI-6120, HI-6121 ...
Page 31
... IWA IBR R 0 12,11 ----- R 0 HI-6120, HI-6121 LSB Index Equal Zero Interrupt. If the IXEQZ bit is set in the Interrupt Enable register and the subaddress descriptor Control Word allows the IXEQZ interrupt, this bit is asserted for (a) subaddresses using indexed buffer mode when the index decrements from (b) subaddresses using circular buffer modes when the pre-determined number of messages has been transacted ...
Page 32
... EECKF R 0 HI-6120, HI-6121 Message Error Interrupt. If the MERR bit is set in the Interrupt Enable register, this bit is asserted when a message error is detected. Errors can be caused by Manchester encoding problems or protocol errors. The INTMES output is asserted and the Interrupt Log is updated. Not used. ...
Page 33
... SVCREQ R/W 7-4 ----- R HI-6120, HI-6121 RAM Initialization Fail Interrupt. This bit is asserted after auto-initialization if an initialized RAM location does not match its 2 corresponding serial EEPROM locations. Because the RAMIF bit is always set in the Interrupt Enable register, the INTHW output is asserted and the Interrupt Log is updated. ...
Page 34
... If the MCOPT3-MCOPT2 bits equal 10, the re- ceived data word is automatically loaded into the Time-Tag counter if the low order bit of the received data word (bit 0) equals 1. For non-broadcast MC17 commands, the counter load occurs before status word transmission. HI-6120, HI-6121 Function Busy (global). ...
Page 35
... Interrupt Log Address Register (0x0009) This 16-bit register is Read-Only and is fully maintained by HI-6120/21 logic. The register contains 0x0040 after MR pin master reset but is not affected by SRST software reset. Bits 7:0 contain an address pointer for the 32-word Interrupt Log Buffer located in shared RAM. The value in Interrupt Log Address register bits 7:0 indicates the storage address where interrupt information words will be stored for the next occurring interrupt, 0x40 - 0x5E ...
Page 36
... HI-6121 Serial Peripheral Interface (SPI). See data sheet section, ”Host Serial Peripheral Interface (SPI)” for further details. For HI-6120 devices, writes to this address have no effect; the address reads back 0x0000 if a host read cycle occurs. ...
Page 37
... LBFA, LBFB R TTINT1 R/W 0 HI-6120, HI-6121 Function Broadcast Command Received Interrupt. When this bit is asserted, interrupts are globally enabled for each broad- cast message to subaddresses in which the Descriptor Control Word allows the IBR interrupt. When this bit is asserted, occurrence of an IBR event causes INTMES output assertion (if the IBR bit is set in the com- mand’ ...
Page 38
... This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset, but is not affected by SRST software reset. This register has two functions associated with the free-running Time-Tag counter: HI-6120, HI-6121 Function Time-Tag Interrupt 0. If this bit is logic 1, the INTHW interrupt output is asserted and the TTINT0 ...
Page 39
... Select register to determine whether inactive Bus B is selected for “transmitter shutdown” or “transmitter shutdown override”. If the data word matches the value stored in the Bus B Select register and MCOPT4 equals 0, the device automatically fulfills MC20 “transmit shutdown” or MC21 “shutdown override” without host assistance: If the mode HI-6120, HI-6121 7 6 ...
Page 40
... 11-6 ----- R BLBFA BLBFB HI-6120, HI-6121 LSB Function Transmitter A Shutdown. Transmitter B Shutdown. These read-only bits are set when the corresponding bus transmitter was disabled by assertion of the bus TXINHA or TXINHB input pin fulfill- ment of a “transmitter shutdown” mode command MC4 or MC20. Refer to ...
Page 41
... This register controls RAM built-in self-test, and transceiver loopback testing. Bits are Read Only. The re- maining bits in this register are Read-Write but can be written only when the TEST input pin is high. If TEST = 0, these bits will read back 0x0000. HI-6120, HI-6121 Function BIST Memory Test Fail (see Section 5.20). ...
Page 42
... NOTE: ‘Reset’ refers to bit value following either Master Reset (MR) or software reset. Bit No. Mnemonic R/W Reset Function 15 FRAMA R/W 14 RBFFAIL R/W 13,12,11 RBSEL2:0 R/W HI-6120, HI-6121 LSB Full RAM Access Enable. During normal operation, some bits in certain RAM locations (e.g., Descrip- 0 tor Table Control Words) cannot be written by the host ...
Page 43
... RBSTRT R/W 0 HI-6120, HI-6121 Description of the RAM BIST “PATTERN” test selected when register bits RBSEL2:0 = 001: Note: Test read /write accesses to addresses 0x0000 - 0x001F involve 32 RAM locations not accessible to the host. These accesses do not affect the host-accessible registers, overlaying the same address range. ...
Page 44
... LBFAIL R 0 HI-6120, HI-6121 RAM BIST Pass. Device logic asserts this bit when the selected RAM test completes without error. This bit is automatically cleared when RBSTRT bit 10 is set. RAM BIST Fail. Device logic asserts this bit when failure occurs while performing the selected RAM test ...
Page 45
... This 16-bit register is Read-Only. This register is cleared after MR pin master reset, but is not affected by SRST software reset. Data is written to this register when performing digital loopback testing. See Test Control Register, 0x0016, for additional information. LOOPBACK TEST RECEIVE DATA REGISTER15 MSB HI-6120, HI-6121 ...
Page 46
... Mode Codes 17, 20 and 21 with T/R bit = 1 The UMCINV bit in Configuration Register 1 determines how these undefined mode commands are handled by the HI-6120/21. If the UMCINV configuration bit equals 1, the undefined mode commands are treated as invalid. They are not recognized by the device. There is no terminal response and status is not updated. If the UMCINV configuration bit equals 0, the 22 undefined mode commands are considered valid ...
Page 47
... Command Word transmit command addressed to a single transmitting terminal. Command Word 2 cannot be broadcast address RT31. The HI-6120 automatically detects and handles commands, except when either command word contains a subad- dress field equal to 0x0 or 0x1F. Either subaddress val- ue indicates a mode code command ...
Page 48
... COMMAND ILLEGALIZATION TABLE The following pages describe various structures resid- ing in the RAM shared between the host and HI-6120 or HI-6121 command processing logic. The host initializes these structures to control the terminal’s response to re- ceived commands. The first structure described is the command Illegalization Table used for “ ...
Page 49
... Figure 4. Deriving the Illegalization Table Address From the Received Command Word HI-6120, HI-6121 Figure 6 shows individual bit locations in the Illegaliza- tion Table for broadcast and non-broadcast variants of all mode commands defined by MIL-STD-1553B. Loca- tions are also identifed for reserved mode codes and undefined mode code commands ...
Page 50
... Illegalization Table Comprised of 32 2-word Blocks per Quadrant Figure 5. Fixed Address Mapping for Illegalization Table Figure 6 summarizes the 16 Illegalization Table locations for mode commands. These locations are scattered through- HI-6120, HI-6121 RT Address Tx Mode Codes Address Tx Mode Codes Addr Tx SA30 Word Counts ...
Page 51
... Without Data RAM Address Figure 6. Summary of Illegalization Table Addresses for Mode Code Commands HI-6120, HI-6121 and all undefined mode commands are illegal: If all de- fined receive mode commands are legal, the eight table entries for receive mode commands would be: 0x01BF and 0x0181 = 1111 1111 1100 1101 = 0xFFCD ...
Page 52
... Interrupt Identification Word and Interrupt Ad- dress Word. HI-6120, HI-6121 The Interrupt Identification Word (IIW) identifies the oc- curring interrupt type using a word format identical to the Pending Interrupt Register. Upon update, all bits except the occurring interrupt type bit(s) are reset ...
Page 53
... IIW and IAW to offset locations 00000 and 00001 respectively. The device increments the ring buffer pointer after each word is stored, storing interrupt HI-6120, HI-6121 information sequentially in the ring buffer. Information words for the sixteenth interrupt are stored in offset locations 0x1E and 0x1F (buffer addresses 0x005E and 0x005F) and the Interrupt Log Address “ ...
Page 54
... Interrupt Address Word 0x0040 INTERRUPT 1 Interrupt Information Word Figure 7. Fixed Address Mapping for Interrupt Log Buffer HI-6120, HI-6121 The Interrupt Log Address Register points to this address after Interrupt 15 event occurs. Upon Interrupt 16 completion, device logic reinitializes the log address pointer to 0x0040 before Interrupt 17 is processed ...
Page 55
... Control Word. Update will differ based on the chosen data buf- fer method. Reading the descriptor table can differ from other RAM accesses. For HI-6120, see Section 15.1.1. For HI-6121, see Sections 15.2.5 and 15.2.7. HOLT INTEGRATED CIRCUITS ...
Page 56
... Subaddress 1 Block Subaddress 0 Block 0x0200 Figure 8. Address Mapping for Descriptor Table (assumes table base address = 0x0200) HI-6120, HI-6121 Descriptor Word 4 for Tx MC30 Descriptor Word 3 for Tx MC30 Descriptor Word 2 for Tx MC30 Control Word for Tx MC30 Descriptor Word 4 for Rx MC30 ...
Page 57
... NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un- changed unless specifically indicated by an “SR” value. Bit No. Mnemonic R/W Reset Function 15 IXEQZ 0 HI-6120, HI-6121 Word Count Command WC4:0 Sync P Descriptor Address Format Depends On Command Word’ ...
Page 58
... BCAST HI-6120, HI-6121 Interrupt When Accessed. If the Interrupt Enable Register IWA bit is high, assertion of this bit enables interrupt generation when the subaddress receives any valid receive com- mand. If enabled, upon completion of command processing, an IWA interrupt is entered in the Pending Interrupt Register, output pin INTMES is asserted, and the interrupt is registered in the Interrupt Log ...
Page 59
... CIR1EN 0 HI-6120, HI-6121 Ping-Pong Enable Acknowledge. This bit is controlled by the device and cannot be written by the host. It only applies if PPEN bit 2 was initialized to logic one by the host after reset, en- abling ping-pong buffer mode for this subaddress. Device logic asserts this bit when it recognizes ping-pong is active for this subaddress ...
Page 60
... NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un- changed unless specifically indicated by an “SR” value. Bit No. Mnemonic R/W Reset 15 IXEQZ 0 14 IWA 0 13 ----- 0 12 MKBUSY 0 HI-6120, HI-6121 ...
Page 61
... PPON 0 7-4 CIR2ZN 0 HI-6120, HI-6121 Function Descriptor Block Accessed. Internal device logic asserts the DBAC bit upon completion of message processing. The host may poll this bit to detect subaddress activity, instead of using host interrupts. This bit is reset to logic zero by MR master reset, SRST software reset or a read cycle to this memory address ...
Page 62
... When Simplified Mode Command Processing is used, the range of active bits is reduced in each receive or transmit mode command Control Word. Interrupt control and response is not affected by the SMCP option. Simplified Mode Command Processing is fully presented in the later data sheet section entitled “Mode Code Commands.” HI-6120, HI-6121 Function Stop Ping-Pong Request. ...
Page 63
... NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un- changed unless specifically indicated by an “SR” value. Bit No. Mnemonic R/W Reset 15 IXEQZ 0 14 IWA 0 HI-6120, HI-6121 ...
Page 64
... Device logic sets this bit when a valid broadcast mode command is received having T/R bit = 0. This bit has no function if the BCSTINV bit is asserted in Configuration Register 1. In this case, RT address 31 commands are not rec- ognized as valid by the HI-6120/21. This bit is reset to logic master reset or SRST software reset. HOLT INTEGRATED CIRCUITS ...
Page 65
... BCAST bits. Following any read cycle to the Control Word address, the DBAC bit is reset. When single-message indexed buffering or ping-pong buffering is used instead of SMCP (Simplified Mode Code Pro- cessing), the transmit mode Control Word looks like this: HI-6120, HI-6121 Function Ping-Pong Enable Acknowledge. ...
Page 66
... NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is un- changed unless specifically indicated by an “SR” value. Bit No. Mnemonic RW Reset 15 IXEQZ 0 14 IWA 0 13 IBR 0 HI-6120, HI-6121 ...
Page 67
... Device logic sets this bit when a valid broadcast mode command is received having T/R bit = 1. This bit has no function if the BCSTINV bit is asserted in Configuration Register 1. In this case, RT address 31 commands are not rec- ognized as valid by the HI-6120/21. This bit is reset to logic master reset or SRST software reset. Ping-Pong Enable Acknowledge. ...
Page 68
... PPEN 0 1,0 ----- 0 HI-6120, HI-6121 Function Not Used Stop Ping-Pong Request. The host asserts this bit to suspend ping-pong buffering for this mode code. The host resets this bit to ask the device to re-enable ping-pong. The device confirms recognition of ping-pong enable or disable status by writing PPON bit 3 ...
Page 69
... Time-Tag counter when the command is validated. The host initializes the Descriptor Table entry for each subaddress or mode command to select one of four data buffering methods. HI-6120, HI-6121 1. Indexed (Single Buffer) Method (see 11.4). A predetermined number of messages (N) is trans- acted using a single data buffer in shared RAM. ...
Page 70
... The data pointer is located in the receive subad- dress command’s Descriptor Block, fully described later: Data Buffer Hex Address Data pointer equals 0x0500 → 0x0500 HI-6120, HI-6121 Table 7. Summary of Data Buffer Modes. Message Info Suitable for Word ...
Page 71
... This bit is asserted when the Illegalization Table bit corresponding to the received com- 8 ILCMD mand is logic 1. The Illegalization Table should only contain nonzero values when “illegal command detection” is being applied. See section entitled Illegalization Table for further information. HI-6120, HI-6121 ...
Page 72
... Hex Address Data pointer equals 0x0500 → 0x0500 MSB The following bits comprise the transmit subaddress Message Information Word. HI-6120, HI-6121 Word Description Message Information Word 0x0501 Time-Tag Word 0x0502 Data Word 1 0x0503 Data Word 2 0x0504 ...
Page 73
... Receive Mode Command The receive mode command data structure contains a Message Information Word, a Time-Tag Word and may con- tain one Data Word receive mode command has a data word, the device may apply the data as defined by MIL- HI-6120, HI-6121 HOLT INTEGRATED CIRCUITS 73 ...
Page 74
... Gap Error. 13 GAPERR Assertion of this bit indicates bus activity was detected immediately after a received mode data word or that a gap occurred before the data word was received. HI-6120, HI-6121 Word Description Message Information Word 0x0501 Time-Tag Word 0x0502 Mode Data Word ...
Page 75
... This applies to MC16 “Transmit Vector Word”. Notice that the data pointer points to the data structure starting address, not the mode data word. The data pointer is located in the transmit mode command’s Descriptor Block, fully described later: HI-6120, HI-6121 HOLT INTEGRATED CIRCUITS 75 ...
Page 76
... This bit is asserted when the terminal responds to the mode command with BUSY status, 9 WASBSY due to global BUSY bit set in 1553 Status Bits Register, or command-specific MKBUSY bit set in the descriptor table Control Word. No mode data word was transmitted. HI-6120, HI-6121 Word Description Message Information Word 0x0501 Time-Tag Word ...
Page 77
... Not Used. Bus Identification. 5 BUSID If this bit equals zero, message was transacted on Bus A. If bit equals one, it was trans- acted on Bus B. Mode Code. 4-0 MC4:0 This 5-bit field contains the mode code extracted from the command word. HI-6120, HI-6121 HOLT INTEGRATED CIRCUITS 77 ...
Page 78
... Figure general illustration of ping-pong buffer mode. Figure 11 shows a specific example. HI-6120, HI-6121 11.3.2. Ping-Pong Enable / Disable Handshake Because ping-pong messages and host buffer servicing are asynchronous, there is potential for “data collision”. ...
Page 79
... Descriptor Control Word is updated so next message uses other buffer. Buffers are overwritten every other message. Separate buffer for broadcast messages is optional. There is no alternate buffer for successive broadcast messages. Figure 10. Illustration of Ping-Pong Buffer Mode HI-6120, HI-6121 Data Word 32 Data Words 2-31 Data Word 1 Time-Tag Word ...
Page 80
... Word DPB bit does not toggle after broadcast message completion. Option 1 Setup: At initialization, host asserts the NOTICE2 bit in Configuration Register 1 and sets the HI-6120, HI-6121 IBR (Interrupt Broadcast Received) bit in descriptor Control Word(s). The IBR bit is asserted in the Interrupt Enable Register. When a broadcast command is received, message in- formation and data is stored in the broadcast data buffer and an INTMES interrupt is generated ...
Page 81
... Message # broadcast command, while the other three messages are non-broadcast. Notice that the broadcast message does not affect DPB bit, but the following message resets BCAST bit. The interspersed broadcast command does not affect alternation between Buffer A and Buffer B. Figure 11. Ping-Pong Buffer Mode Example for a Receive Subaddress HI-6120, HI-6121 0x0565 0x0547 - 0x0564 0x0546 ...
Page 82
... INDX counter decrement does not occur if the command was illegalized or if INDX already equals zero. Once HI-6120, HI-6121 INDX equals zero, further commands will overwrite the last-written data buffer block and the data pointer value is not updated after successful message completion. ...
Page 83
... Option 2 for Index Mode Broadcast Messages: The second alternative stores both broadcast and non- HI-6120, HI-6121 broadcast message information in data buffer A. Op- tional IBR interrupts can signal arrival of broadcast mes- sages. The RT handles broadcast messages just like ...
Page 84
... Upon successful message completion, if non-zero the INDX count in Descriptor Word 3 is decremented. If decremented result is non-zero, Data Pointer A is adjusted so next message is stored above just-completed message. If decremented INDX is zero, Data Pointer A remains static and IXEQZ interrupt occurs if enabled in Control Word. Figure 12. Illustration of Indexed Buffer Mode HI-6120, HI-6121 Increasing Memory Address Message B’ ...
Page 85
... Memory Address B’cast Data Pointer INDX Index Count Data Pointer A Control Word Descriptor Block Receive Subaddress Figure 13. Indexed Buffer Mode Example for a Receive Subaddress (broadcast not enabled) HI-6120, HI-6121 Data Word 4 0x050A 0x0509 Data Word 3 Data Word 2 0x0508 0x0507 Data Word 1 ...
Page 86
... EA remain static during message processing. The third word in the descriptor block identifies the current address CA (i.e., last accessed address plus one). The HI-6120, HI-6121 circular buffer wraps to the start address after complet- ing a message that results in CA being greater than or equal to EA increments past EA during message processing, the device will access memory addresses greater than the EA value ...
Page 87
... Circular Buffer Mode 1 does not support NOTICE2 seg- regation of broadcast data, even when the NOTICE2 bit equals 1 in Configuration Register 1. Data from broad- HI-6120, HI-6121 cast and non-broadcast receive commands is stored in the same buffer. The BCAST bit in the Message Infor- mation Word reflects broadcast or non-broadcast status for each stored message ...
Page 88
... Current Address points past End Address, the Current Address is reinitialized to match Start Address and an optional interrupt is generated to notify host that the pre-determined data block was fully transacted. Figure 14. Illustration of Circular Buffer Mode 1 HI-6120, HI-6121 Last Message in Data Block End Address Current ...
Page 89
... Buffer size was purposely sized to yield remaining capacity after 2 full-count messages, to illustrate device behavior. The circular buffer should have a 33-word pad beyond its End Address to deal with buffer overrun without data loss. Figure 15. Circular Buffer Mode 1 Example for a Receive Subaddress HI-6120, HI-6121 (1 + Data Word 32 address) ≥ End Address. 0x0565 ...
Page 90
... The MIBA pointer is not updated if message error occurred, if the Busy status bit was set the command was illegal- HI-6120, HI-6121 ized (for example an illegal word count expressed in the command word.) For these situations, the Message In- ...
Page 91
... HI-6120, HI-6121 initially-zero trailing address bits equal 1 after MIBA is in- cremented once. In our example, MIBA would increment from 0x0FFE to 0x0FFF. When “full count” occurs, the device updates MIBA to the original value (e.g., 0x0F00) and copies the SA starting address value to CA current address register, ready for buffer service by the host. The device optionally generates a “ ...
Page 92
... MIBA points to the next location in the message information buffer and CA points to the next lo- HI-6120, HI-6121 cation in the data buffer. If the completed message is the last message in the block, the CA current (data) address and MIBA message Information pointers are reinitialized to their base address values ...
Page 93
... Segregated storage for data and message information simplifies host loading / offloading of buffered data. Descriptor MIB Address tracks number of messages. Full count occurs when N initialized 0-bits become N 1-bits. When full number of messages in block is transacted, an optional interrupt is generated to notify host. Figure 16. Illustration of Circular Buffer Mode 2 HI-6120, HI-6121 Last Message in Data Block Increasing ...
Page 94
... Example is set to successfully transact four 32 data word receive messages, then generate IXEQZ interrupt for host. The data buffer requires minimal processing by host because message information words are stored separately in MIB. Figure 17. Circular Buffer Mode 2 Example for a Receive Subaddress HI-6120, HI-6121 0x057F Data Word 32 ...
Page 95
... Note: Mode command MC0 “dynamic bus control” can- not be implemented in the device since the HI-6120/21 cannot act as a Bus Controller. Therefore, the “dynamic bus control acceptance” status bit cannot be set in the outgoing status word from this device ...
Page 96
... HI-6120, HI-6121 decimal are stored within the Descriptor Table itself. This is explained next. MIL-STD-1553 Defined Function Undefined mode commands when T/R bit = 0 Dynamic Bus Control Synchronize (without data) Transmit Status Word Initiate Self-Test Transmitter Shutdown ...
Page 97
... Illegalization Table bit equal to 1, and re- sponds “in form” when the Table bit equals zero. The “in form” response for reserved mode commands 16 through 31 transacts a received or transmitted data word. 3. HI-6120/21 cannot fulfill Bus Control duties. HI-6120, HI-6121 MIL-STD-1553 Defined Function ...
Page 98
... RAM. Instead, each 4-word descriptor block itself contains the message information word, the time- tag word and the data from the most recent occurrence of each mode command: HI-6120, HI-6121 Descriptor Word 1 Mode Command Control Word Descriptor Word 2 Message Information Word Descriptor Word 3 Time-Tag Word ...
Page 99
... Current Control Word Address register. Both registers maintain their loaded values until the next valid command to the terminal is decoded. HI-6120, HI-6121 13.2. Host Interrupt Generation Interrupts are output signals notifying the host when predetermined events have occurred during terminal op- eration ...
Page 100
... Words identify type of interrupt event. Bit assignments match those used in the Pending Interrupt Register. The host or subsystem reads the IIW to determine which type of interrupt occurred. The Interrupt Identification Word is defined in Table 11. HI-6120, HI-6121 Table 11. Interrupt Identification Word IIW - Interrupt Identification Bit Interrupt ...
Page 101
... If the Operational Status register AUTOEN bit reads low, auto-initialization is bypassed. The host must ini- tialize the terminal as follows: HI-6120, HI-6121 a. The device asserts the READY output pin. This state change indicates the host can begin post- MR reset initialization of registers and RAM struc- tures ...
Page 102
... EEPROM locations corresponding to device RAM ad- dress 0x0020 must contain the expected checksum value. The serial EEPROM used for auto-initialization should be fully written to cover the HI-6120/21 upper address limit of 0x7FFF (or 0x03FF, depending on the state of the EE1K input pin). Ideally the EEPROM image ...
Page 103
... Alternate BIT Word Register 0x0016 Test Control Register 0x0017 BIST Control Register 0x0018 Loopback Test Transmit Data Register 0x0019 Loopback Test Receive Data Register 0x0020-0x001F HI-6120, HI-6121 Device Register Time-Tag Register Reserved Reserved HOLT INTEGRATED CIRCUITS 103 Contents Contents after MR after SRST ...
Page 104
... Upon SRST reset, the DBAC, DPB, MKBUSY and BCAST bits are reset for each of the 128 Control Words in the primary Descriptor Table which starts at address 0x0200. If secondary Descriptor Tables are used (above address 0x0400), the host must perform any necessary table reconfiguration after SRST reset. HI-6120, HI-6121 RAM Structure Host-Assigned Data Buffers ...
Page 105
... Remote Terminal” mode command MC8 is affected by host response speed and application complexity. 14.4. Serial EEPROM Programming Utility The HI-6120 or HI-6121 can program a serial EEPROM via the dedicated EEPROM SPI port for subsequent auto-initialization events. The device copies host-config- ured registers and RAM (configuration tables and pos- sibly data buffers) to serial EEPROM ...
Page 106
... A deliberate series of events initiates copy of data from HI-6120 or HI-6121 to serial EEPROM. This reduces the likelihood of accidental EEPROM overwrites. This series of events must occur to initiate programming using a fresh host initialization immediately following MR master reset as the basis for EE- PROM copy: With the AUTOEN, TXINHA and TX- INHB pins in logic zero state, apply MR master reset and wait for READY output assertion ...
Page 107
... A0 (LB) address pin is not used and the BENDI input pin is “don’t care.” 15.1.1. Bus Wait States and Data Prefetch The HI-6120 has a WAIT output pin that tells the host to add wait states when additional access time is needed during bus read cycles. For compatibility with different host processors, the state of the WPOL input pin sets the WAIT output as active high or active low ...
Page 108
... HI- 6120) to match the faster read cycle time for prefetched data, while the HI-6120 WAIT output adds one or more additional wait states for the slower initial read cycle. Timing diagrams for bus read and write operations are shown in Section 17.5. Separate diagrams show “ ...
Page 109
... The SPI command set includes directly-addressed read and write commands for registers 0 through 15. The 8-bit pattern for these commands has the general form HI-6120, HI-6121 where RRRR is the 4-bit register address, and the most significant bit, W signifies Write when 1, or Read when ...
Page 110
... SO CE Figure 19. Single-Word (2-Byte) Read From RAM or a Register SCK SPI Mode 0 MSB SI Command Byte High Figure 20. Single-Word (2-Byte) Write To RAM or a Register HI-6120, HI-6121 LSB MSB LSB MSB Data Byte ...
Page 111
... Command Write Operation add 1 to pointer then write addressed 0xC8 location HI-6120, HI-6121 15.2.5. Data Prefetch for SPI Read Cycles Data prefetch is a technique used by the HI-6121 to speed up host multi-word read access to registers or RAM. Prefetching occurs when HI-6121 logic accesses data before it is actually needed. Because register or ...
Page 112
... These six commands can be used to read or write a single location, or may be used to start a multi-word read or write that uses the pointer’s auto-increment feature. HI-6120, HI-6121 When some or all subaddress or mode commands are not programmed to trigger host interrupts, a different single-byte SPI command may be useful if polling the Descriptor Table for message activity ...
Page 113
... Control Word next) ---- <data> data from 0x0203 (SCK stops and /CS is then negated) HI-6120, HI-6121 addressed word is transferred by SPI to the host, the HI- 6121 continues to read and transmit words from sequen- tial RAM memory addresses, as long as the host con- tinuously asserts chip select while providing SCK serial clock pulses ...
Page 114
... MAP then read addressed location ---- <data> data from 0x03FC (SCK continues afterward) ---- <data> data from 0x03FD (SCK continues afterward) ---- <data> data from 0x03FE (SCK continues afterward) ---- <data> data from 0x03FF (SCK continues afterward) TABLE ENDS HI-6120, HI-6121 HOLT INTEGRATED CIRCUITS 114 ...
Page 115
... Read Register 0x38 Read Register 0x3C Read Register 15 HI-6120, HI-6121 Command Bits ...
Page 116
... Read then add 4 to the current address pointer value in register 15. Write storage address of last-written Interrupt Address Word to the address pointer in register 0x58 R 15, then read the Interrupt Address Word from the Interrupt Log buffer. Decrement memory address pointer after read operation. HI-6120, HI-6121 Special Purpose Commands HOLT INTEGRATED CIRCUITS 116 ...
Page 117
... Terminal is using “illegal command detection” and command is legal OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response). ** Terminal is using “illegal command detection” and command is illegal. HI-6120, HI-6121 Bits Updated in Descriptor Control Word ...
Page 118
... If RT-RT Command Word 1 is T/R bit = 0, or CW2 broadcast (RT31) also set subaddress equals the BCR status bit (mode code), or CW2 has same RT address as CW1. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set. DPB bit toggles. BCAST bit updated. DBAC bit set. ...
Page 119
... This only applies for the UMCINV bit in undefined mode codes: Configuration MC0 to MC15 with T Register 1 equals 1. MC16,18 & 19 with T MC17,20 & 21 with T HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit updated DPB bit toggles. DBAC bit set. ...
Page 120
... Word 4 in Descriptor Table. * Terminal is using “illegal command detection” and command is legal OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response). ** Terminal is using “illegal command detection” and command is illegal. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set ...
Page 121
... Descriptor Word 4. * Terminal is using “illegal command detection” and command is legal OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response). ** Terminal is using “illegal command detection” and command is illegal. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set ...
Page 122
... If broadcast, the BCR bit valid receive command in Status Word is also (MKBUSY bit set in the set. command’s Descriptor Table control word.) HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit updated. DPB bit toggles. No change to superseded command’ ...
Page 123
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set ...
Page 124
... Status Illegalization Table Word. bit equals Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit reset. ...
Page 125
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set ...
Page 126
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set ...
Page 127
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 128
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 129
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 130
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 131
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 132
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 133
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set ...
Page 134
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 135
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 136
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 137
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset ...
Page 138
... No terminal response, OR the message is ignored. T/R bit equals 0 and No Status Word change. UMCINV bit in Config. (mode code is undefined Register 1 equals 1 *** when T/R bit equals 0) HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset. BCAST bit reset. DPB bit toggles. No Change HOLT INTEGRATED CIRCUITS ...
Page 139
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set ...
Page 140
... UMCINV bit in Config. If not broadcast, transmit Register 1 equals 0. Status Word. If broadcast, The Illegalization Table set the BCR status bit and bit equals 0 * suppress status response. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit reset. BCAST bit reset. DPB bit toggles. No Change DBAC bit set ...
Page 141
... Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set ...
Page 142
... Set the Message Error word is not followed by (ME) status bit. a contiguous data word If broadcast, set the (missing data word) BCR status bit. HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit reset. DPB bit toggles. DBAC bit set. ...
Page 143
... Set the Message Error is addressed to RT31 (ME) and BCR status bits. * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” HI-6120, HI-6121 Bits Updated in Descriptor Control Word DBAC bit set. ...
Page 144
... Pull Up / Pull Down Current Min. Output Voltage (HI) Max. Output Voltage (LO) RECEIVER (Measured at Point “AD” in Figure 26 unless otherwise specified) Input Resistance Input Capacitance Common Mode Rejection Ratio Input Level HI-6120, HI-6121 17.2. Recommended Operating Conditions Operating Supply voltage ( Operating Temperature Range ...
Page 145
... Operating Temperature Range (unless otherwise stated Parameters HI-6121 INTERFACE TIMING (SPI Host Bus Interface) SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge HI-6120, HI-6121 Symbol Test Conditions V ICM V 1 Mhz Sine Wave (Measured THD at Point “ ...
Page 146
... SCKH SCKL SCLK SO Hi Impedance Figure 21. HI-6121 Host Bus Interface Timing Diagram 17.5. AC Electrical Characteristics ― HI-6120 Host Bus Interface Timing Parameters HI-6120 INTERFACE TIMING (Parallel Host Bus Interface) HI-6120, HI-6121 SERIAL INPUT TIMING DIAGRAM t CES t DH MSB SERIAL OUTPUT TIMING DIAGRAM ...
Page 147
... Successive writes to sequential addresses have same timing. A15 WAIT D15:0 All timing intervals equal 0 ns MIN unless otherwise indicated. Figure 22. Register and RAM Write Operations for BTYPE = 1 HI-6120, HI-6121 OE Output Enable and WE Write Enable) ADDRESS ...
Page 148
... Successive writes to sequential addresses have same timing. A15 STR WAIT D15:0 All timing intervals equal 0 ns MIN unless otherwise indicated. Figure 23. Register and RAM Write Operations for BTYPE = 0 HI-6120, HI-6121 Read/Write Strobe STR and R/ ADDRESS INACT ...
Page 149
... WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted. ...
Page 150
... WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted. ...
Page 151
... Point “AD” 35Ω Figure 26. MIL-STD-1553 Direct Coupled Test Circuits TRANSMITTER Tx Data from Manchester Encoder TXINHA/B 52.5Ω (.75 Zo) 35Ω (.5 Zo) 52.5Ω (.75 Zo) Figure 27. MIL-STD-1553 Transformer Coupled Test Circuits HI-6120, HI-6121 1:2.5 BUSA/B BUSA/B Isolation Transformer 2.5:1 55Ω 55Ω Isolation Transformer Point “AT” 1:2.5 ...
Page 152
... See page 1 for HI-6121, 52-Pin PQFP Package Configuration. 20.1. HI-6121PCx (64-pin QFN) GND COMP CE MODE SCK SO VCC MCLK GND 10 RTA0 11 RTA1 12 RTA2 13 MR RTA3 15 RTA4 16 HI-6120, HI-6121 Condition θ C/W) ja Mounted on 52.7 circuit board Mounted on 60.9 circuit board Heat sink pad 31.1 unsoldered Heat sink pad 22 ...
Page 153
... HI-6120PQx (100-pin QFN) VCC - 1 GND - 2 D12 - 3 D13 - 4 D14 - 5 D15 - 6 COMP - MODE - 9 STR - 10 VCC - 11 BTYPE - 12 MCLK - 13 GND - 14 WAIT - RTA0 - 17 RTA1 - 18 RTA2 - RTA3 - 21 RTA4 - HI-6120, HI-6121 TOP VIEW HOLT INTEGRATED CIRCUITS 153 BENDI 72 - TEST ...
Page 154
... PART NUMBER PART NUMBER 6121 PART NUMBER Blank F PART NUMBER PART NUMBER PC PQ HI-6120, HI-6121 LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW - + - +125 C ...
Page 155
... DS6120, Rev. NEW 11/24/09 Rev. A 6/15/10 Rev. B 11/18/10 HI-6120, HI-6121 Description of Change Initial Release Datasheet format change (Table of Contents, List of Figures, List of Tables and cross- references added). Inserted new sections to clarify Data Prefetch operations. Minor typos corrected. Corrected Power Supply Current and device Power Dissipation values and added explanatory notes ...
Page 156
... Standard 95) 64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) .354 BSC (9.00) .354 Top View BSC (9.00) .039 max (1.00) HI-6120, HI-6121 .394 BSC SQ (10.0) .063 typ (1.6) See Detail A .055 .002 ± (1.4 .05) ± Heat sink pad on bottom of package. Heat sink must be left floating or connected NOT connect to GND. .281 ± ...
Page 157
... PLASTIC QUAD FLAT PACK (PQFP) .630 BSC SQ (16.0) .039 typ (1.0) .059 .004 ± (1.50 ± .10) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-6120, HI-6121 .551 BSC SQ (14.0) .008 (0.20) See Detail A .055 .002 ± (1.40 ± .05) .003 (0.08) HOLT INTEGRATED CIRCUITS ...