HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 14

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

WAIT or WAIT
R/W or WE
STR or OE
A15:1 and
A0 (LB)
BTYPE
WPOL
D15:0
BWID
Pin
Function
OUTPUT
INPUTS
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
Description
Tri-state data bus for host read/write operations upon registers and shared RAM.
Internal 50KΩ pull-down resistors. All read/write operations transact 16 bit words,
but bus width can be configured for 8 or 16 bits. For 8 bit bus width, pins D15:8
are not connected; each 16-bit word is transacted as a pair of upper and lower
byte operations, with data presented sequentially on pins D7:0. For compatibility
with different host processors, when byte transfers are enabled the BENDI input
pin sets whether the low order byte is transferred before the high order byte, or
vice versa.
Address bus for host read/write operations upon registers and shared RAM. For
16-bit bus width, address bit A0 (LB) from the host is not used. For 8-bit bus width,
bit A0 equals 0 during the first byte read/write access; while A0 equals 1 during
the second byte access.
Configuration pin for host bus width. Internal 50KΩ pull-up resistor. High selects
16-bit bus width, low selects 8-bit bus width.
Configuration pin for host bus read/write control signal style. Internal 50KΩ pull-up
resistor. High selects “Intel style” using separate read strobe OE (output enable)
and write strobe WE. Low selects “Motorola style” using combined read/write
strobe STR and read/write select signal, R/W.
R/W (read/write) signal when BTYPE pin is low, or WE (write enable) when
BTYPE pin is high. Internal 50KΩ pull-up resistor. Used for host read or write ac-
cesses to device RAM or registers. Important: This pin or the CE pin should be
high during all address transitions.
When BTYPE pin is low, common STR (read/write strobe). When BTYPE pin is
high, OE (output enable). Internal 50KΩ pull-up resistor. Used for host read or
write accesses to device RAM or registers.
Host bus read cycle “wait” output. For compatibility with different host processors,
this output can be made active high or active low, set by the state of the WPOL
input pin. The WAIT output may be ignored when the host processor’s read cycle
time is sufficiently slow to meet worst case (slowest) read cycle timing for this
device, or when wait cycles have been enabled from the processor. The WAIT
output is useful when the host processor runs at high clock rates and/or when
processor read wait states do not provide adequate timing margin for worst case
(slowest) read cycle timing for this device. See Section 15.1 on page 107 for further
information.
Configuration pin for WAIT output polarity. Internal 50KΩ pull-up resistor. When
WPOL is low, the “wait” output is active low (WAIT). When WPOL is high, the
“wait” output is active high (WAIT). The HI-6120 uses pre-fetching to speed up
any series of reads from successive addresses. As long as successive reads are
sequential, only the first word’s read cycle generates a WAIT (WAIT) output. No
WAIT is generated for following words read.
Table 2. Pin Descriptions (HI-6120 only)
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
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