HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 150

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

A0 LB
D15:0
A15:1
A15:1
R / W
WAIT
R / W
WAIT
using BTYPE = 0 (”Motorola Style” - Single
using BTYPE = 0 (”Motorola Style” - Single Read/Write Strobe
D7:0
STR
STR
After first byte is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential.
WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses.
This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster
successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted.
After first word is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential.
WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses.
This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster
successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted.
CS
CS
t
t
WAS
WAS
Figure 25. Register and RAM Read Operations for BTYPE = 0
showing two successive words read from sequential addresses
High-Z
High-Z
HOST READ IN DUAL-BYTE MODE (8-BIT BUS WIDTH)
HOST READ IN WORD MODE (16-BIT BUS WIDTH)
All timing intervals equal 0 ns MIN unless otherwise indicated.
All timing intervals equal 0 ns MIN unless otherwise indicated.
showing 2 bytes read for a single 16-bit word
ADDRESS
t
W
t
t
t
NSR
NSR
W
HOLT INTEGRATED CIRCUITS
ADDRESS
BYTE 0
HI-6120, HI-6121
WORD
Read/Write Strobe
t
t
INACT
INACT
150
High-Z
High-Z
ADDRESS + 1
STR
STR
t
t
SR8
SR16
BYTE 1
WORD
and R/
and R/
W
W
t
t
INACT
INACT
Direction Select)
Direction Select)
High-Z
High-Z
STR assertion
for the next
Read or Write
STR assertion
for the next
Read or Write