HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 31

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

(enabled at reset) should reside at address space 0x0200 to 0x03FF. Other tables (if used) could begin at address
multiples of 0x0200, like 0x0400 and 0x0600. Bit 15 and bits 8:0 cannot be set and will always read logic 0. Thus a
value written by the host must equal or exceed 0x200.
5.7.
This 16-bit register is Read-Only. If the corresponding bit is set in the Interrupt Enable Register when a predetermined
interrupt-causing event occurs, these actions occur: (1) a pending interrupt bit is set in this register, (2) the INTMES
or INTHW output is asserted, depending on interrupt type, (3) the interrupt is registered in the Interrupt Log. If the cor-
responding bit is reset in the Interrupt Enable Register when a predetermined interrupt-causing event occurs, there is
no reaction. To simplify host interrupt management, when the host reads this register, the Pending Interrupt Register
automatically resets to 0x0000 and (if level interrupts are enabled by the INTSEL configuration bit) the INTMES and/or
INTHW output pins are automatically negated. For further information on interrupt behavior, also see descriptions for
Interrupt Enable register and Interrupt Log Address register, and refer to the later section entitled “Interrupt Manage-
ment”.
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset.
Bit No. Mnemonic R/W Reset Function
MSB
12,11
15
14
13
15 14 13 12 11 10 9
Pending Interrupt Register (0x0006)
IXEQZ
IWA
IBR
-----
X
X
R
R
R
R
X
8
0
0
0
0
7
6
Index Equal Zero Interrupt.
If the IXEQZ bit is set in the Interrupt Enable register and the subaddress
descriptor Control Word allows the IXEQZ interrupt, this bit is asserted for (a)
subaddresses using indexed buffer mode when the index decrements from 1
to 0, or (b) subaddresses using circular buffer modes when the pre-determined
number of messages has been transacted. The INTMES output is asserted
and the Interrupt Log is updated.
Interrupt When Accessed.
If the IWA bit is set in the Interrupt Enable register and the subaddress de-
scriptor Control Word allows the IWA interrupt, this bit is asserted each time a
valid legal message is transacted for the subaddress. The INTMES output is
asserted and the Interrupt Log is updated.
Broadcast Command Received Interrupt.
If the IBR bit is set in the Interrupt Enable register and the subaddress de-
scriptor Control Word allows the IBR interrupt, this bit is asserted each time a
valid legal broadcast message is transacted for the subaddress. The INTMES
output is asserted and the Interrupt Log is updated.
Not used.
5
HOLT INTEGRATED CIRCUITS
4
HI-6120, HI-6121
3
2
1
0
31
LSB