HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 35

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

5.10. Interrupt Log Address Register (0x0009)
This 16-bit register is Read-Only and is fully maintained by HI-6120/21 logic. The register contains 0x0040 after MR
pin master reset but is not affected by SRST software reset. Bits 7:0 contain an address pointer for the 32-word
Interrupt Log Buffer located in shared RAM. The value in Interrupt Log Address register bits 7:0 indicates the storage
address where interrupt information words will be stored for the next occurring interrupt, 0x40 - 0x5E. The value is
always even since two words are stored for each interrupt.
Bits 15:8 contain a count value for the number of interrupts logged (0 - 255) since the Interrupt Log Address Register
was last read. The count increment stops at 255. Bits 15:8 are reset automatically after this register is read by the host.
To help the host process interrupts, the device maintains information from the 16 most recent interrupts in a 32-word
ring buffer in shared RAM, found at address range 0x0040 to 0x005F. Each interrupt stores two information words:
the Interrupt Identification Word (IIW) identifies the interrupt type(s) that occurred; the Interrupt Address Word (IAW)
identifies the interrupt source. For interrupts that result from message processing, the IAW contains the 16-bit address
of the command’s Control Word in the Descriptor Table. For hardware interrupts, the IAW value is 0x0000.
After MR master reset, the device automatically resets this register to 0x0040, an interrupt count of zero and log ad-
dress of 0x40. During terminal operation, the host can read bits 15:8 to see the number of interrupts logged in the
buffer since the last read operation upon the register. Information words for the sixteenth interrupt are stored in buffer
addresses 0x005E and 0x005F, and the Interrupt Log Address “rolls over” to read 0x40, where interrupt information for
the seventeenth interrupt will be stored. For further information on interrupts, see descriptions for the Interrupt Enable
register, the Pending Interrupt register, and see the later section entitled “Interrupt Management”.
5.11. Current Message Information Word Address Register (0x000A)
This 16-bit register is Read-Only and is fully maintained by the device. This register is cleared after MR pin master
reset, but is not affected by SRST software reset. Also see “Current Control Word Address” register, 0x0004.
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset.
Bit No. Mnemonic R/W Reset Function
MSB
MSB
15-0
15 14 13 12 11 10 9
15 14 13 12 11 10 9
A
C
MIWA15:0 R/W
A
C
CURRENT MSG INFO WORD ADDRESS 15:0
A
C
INTERRUPT
COUNT 7:0
A
C
A
C
A
C
A
C
A
C
8
8
0
A
0
7
7
A
1
6
6
Current Message Information Word Address Register
This register contains the data buffer address for the last command’s Mes-
sage Information Word, or MIW, corresponding to the current command stored
in the Current Command Register (0x0003). This register is updated 5us after
the ACTIVE output is asserted. Bit 15 is MSB.
INTERRUPT LOG
A
ADDRESS 7:0
0
5
5
HOLT INTEGRATED CIRCUITS
A
A
4
4
HI-6120, HI-6121
A A
A
3
3
A
2
2
A
A
1
1
A
0
0
0
35
LSB
LSB