E28F320J5100 Intel, E28F320J5100 Datasheet - Page 13

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

NOTE:
1.
2.
3.1
Information can be read from any block, query,
identifier codes, or status register independent of
the V
Upon initial device power-up or after exit from
reset/power-down mode, the device automatically
resets to read array mode. Otherwise, write the
appropriate read mode command (Read Array,
Read Query, Read Identifier Codes, or Read Status
Register) to the CUI. Six control pins dictate the
data flow in and out of the component: CE
CE
enabled (see Table 2, Chip Enable Truth Table ),
and OE# must be driven active to obtain data at the
outputs. CE
selection controls and, when enabled (see Table 2,
Chip Enable Truth Table ), select the memory
device. OE# is the data output (DQ
and, when active, drives the selected memory data
onto the I/O bus. WE# must be at V
3.2
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
2
PRELIMINARY
CE
See Application Note AP-647 Intel StrataFlash™
Memory Design Guide for typical CE configurations.
For single-chip applications CE
strapped to GND.
, OE#, WE#, and RP#. The device must be
V
V
V
V
V
V
V
V
PEN
IH
IH
IH
IH
IL
IL
IL
IL
2
Table 2. Chip Enable Truth Table
voltage. RP# can be at either V
Read
Output Disable
0
, CE
CE
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IL
IL
IL
IL
1
1
, and CE
CE
V
V
V
V
V
V
V
V
IL
IH
IL
IH
IL
IH
IL
IH
0
2
and CE
2
INTEL
are the device
IH
0
IH
–DQ
.
), the device
1
®
Disabled
Disabled
Disabled
Disabled
DEVICE
Enabled
Enabled
Enabled
Enabled
can be
0
IH
–DQ
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
15
(1,2)
or V
) control
0
, CE
15
HH
are
.
1
,
3.3
CE
Table 2, Chip Enable Truth Table ) and place it in
standby mode which substantially reduces device
power consumption. DQ
in a high-impedance state independent of OE#. If
deselected during block erase, program, or lock-bit
configuration, the WSM continues functioning, and
consuming
completes.
3.4
RP# at V
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off numerous internal circuits. RP# must
be held low for a minimum of t
required after return from reset mode until initial
memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
During
configuration modes,
operation. In default mode, STS transitions low and
remains low for a maximum time of t
until the reset operation is complete. Memory
contents being altered are no longer valid; the data
may be partially corrupted after a program or
partially
configuration. Time t
goes to logic-high (V
can be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
program, or lock-bit configuration modes. If a CPU
reset occurs with no flash memory reset, proper
initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s flash memories allow
proper initialization following a system reset through
the use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets
the system CPU.
0
, CE
1
IL
Standby
Reset/Power-Down
block
, and CE
altered
initiates the reset/power-down mode.
active
erase,
after
2
power
can disable the device (see
PHWL
IH
) before another command
0
RP#-low will abort
–DQ
an
program,
is required after RP#
15
until
PLPH
erase
outputs are placed
. Time t
the
PLPH
or
or
operation
+ t
PHQV
lock-bit
lock-bit
PHRH
the
13
is