E28F320J5100 Intel, E28F320J5100 Datasheet - Page 30

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

INTEL
A successful set block lock-bit operation requires
that the master lock-bit be zero or, if the master
lock-bit is set, that RP# = V
the master lock-bit set and RP# = V
SR.4 will be set to “1” and the operation will fail. Set
block lock-bit operations while V
produce spurious results and should not be
attempted.
operation requires that RP# = V
with RP# = V
and the operation will fail. Set master lock-bit
operations with V
results and should not be attempted.
4.12
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits
requires both the Clear Block Lock-Bits command
and V
while the WSM is running or the device is
suspended. See Table 14 for a summary of
hardware and software write protection options.
Clear block lock-bits command is executed by a
two-cycle sequence. A clear block lock-bits setup is
first written. The device automatically outputs status
register data when read (see Figure 12). The CPU
30
Block Erase or
Program
Set or Clear Block
Lock-Bit
Set Master
Lock-Bit
Operation
HH
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
Clear Block Lock-Bits
Command
on the RP# pin. This command is invalid
A
IH
, SR.1 and SR.4 will be set to “1”
successful
IH
< RP# < V
Lock-Bit
Master
X
0
1
X
HH
. If it is attempted with
set
HH
Lock-Bit
HH
Block
. If it is attempted
IH
produce spurious
Table 14. Write Protection Alternatives
X
X
X
master
0
1
< RP# < V
IH
, SR.1 and
V
V
IH
IH
lock-bit
RP#
V
V
V
V
V
V
or V
or V
HH
HH
HH
IH
IH
IH
HH
HH
HH
Block Erase and Program Enabled
Block is Locked. Block Erase and Program Disabled
Block Lock-Bit Override. Block Erase and Program
Enabled
Set or Clear Block Lock-Bit Enabled
Master Lock-Bit Is Set. Set or Clear Block Lock-Bit
Disabled
Master Lock-Bit Override. Set or Clear Block Lock-Bit
Enabled
Set Master Lock-Bit Disabled
Set Master Lock-Bit Enabled
can detect completion of the clear block lock-bits
event by analyzing the STS pin output or status
register bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally
Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a
reliable clear block lock-bits operation can only
occur when V
lock-bits operation is attempted while V
V
successful clear block lock-bits operation requires
that the master lock-bit is not set or, if the master
lock-bit is set, that RP# = V
the master lock-bit set and RP# = V
SR.5 will be set to “1” and the operation will fail. A
clear block lock-bits operation with V
produce spurious results and should not be
attempted.
If a clear block lock-bits operation is aborted due to
V
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-
bits is required to initialize block lock-bit contents to
known values. Once the master lock-bit is set, it
cannot be cleared.
PENLK
PEN
or V
, SR.3 and SR.5 will be set to “1.” A
CC
transitioning out of valid range or RP#
CC
cleared.
and V
Effect
PEN
An
PRELIMINARY
are valid. If a clear block
HH
invalid
. If it is attempted with
IH
Clear
IH
< RP# < V
, SR.1 and
PEN
Block
HH