E28F320J5100 Intel, E28F320J5100 Datasheet - Page 26

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

INTEL
NOTE:
1. The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software
4.3
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Figure 6 retrieve the manufacturer, device, block
lock configuration and master lock configuration
codes (see Table 13 for identifier code values). To
terminate
command. Like the Read Array command, the
Read
independently of the V
V
WSM is off or the device is suspended. Following
the Read Identifier Codes command, the following
information can be read:
26
IH
Offset
(P +C)h
(P +D)h
(P +E)h
should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices.
or V
®
Identifier
HH
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
(1)
Read Identifier Codes
Command
. This command is valid only when the
the
reserved
Length
(bytes)
operation,
01h
01h
Codes
Table 12. Primary Vendor-Specific Extended Query (Continued)
PEN
voltage and RP# can be
V
performance)
V
Reserved for future use
CC
PP
command
write
bits 7–4
bits 3–0
bits 7–4
bits 3–0
Note: This value is 0000h; no V
[Programming] Optimum Program/Erase voltage
Optimum Program/Erase voltage (highest
another
functions
BCD value in volts
BCD value in 100 millivolts
HEX value in volts
BCD value in 100 millivolts
valid
Description
NOTE:
1.
2.
Manufacture Code
Device Code
Block Lock Configuration
Master Lock Configuration
Block Is Unlocked
Block Is Locked
Reserved for Future Use
Device Is Unlocked
Device Is Locked
Reserved for Future Use
A
the identifier codes. The lowest order address line is A
Data is always presented on the low byte in x16 mode
(upper byte contains 00h).
X selects the specific block’s lock configuration code.
See Figure 6 for the device identifier code memory
map.
PP
0
is not used in either x8 or x16 modes when obtaining
pin is present
Table 13. Identifier Codes
Code
32-Mbit
64-Mbit
PRELIMINARY
Address
X
3D:
3E:
00000
00001
00001
00003
0002
StrataFlash™
Memory
(2)
Intel
(1)
(1)
0050h
0000h
®
DQ
DQ
DQ
DQ
(00) 89
(00) 14
(00) 15
DQ
DQ
Data
0
0
0
0
1–7
1–7
= 0
= 1
= 0
= 1
1
.