E28F320J5100 Intel, E28F320J5100 Datasheet - Page 46

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

INTEL
6.5
NOTES:
CE
CE
1.
2.
3.
4.
46
R10
R11
R12
R13
R14
X
1
R1
R2
R3
R4
R5
R6
R7
R8
R9
, or CE
(All units in ns unless otherwise noted)
#
See Figure 16, AC Waveform for Read Operations for the maximum allowable input slew rate.
OE# may be delayed up to t
Enable Truth Table ) without impact on t
Sampled, not 100% tested.
See Figures 13–15, Transient Input/Output Reference Waveform for V
Reference Waveform for V
low is defined as the first edge of CE
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC Characteristics—Read-Only Operations
2
Sym
AVAV
AVQV
ELQV
GLQV
PHQV
ELQX
GLQX
EHQZ
GHQZ
OH
ELFL
ELFH
FLQV
FHQV
FLQZ
EHEL
that disables the device (see Table 2, Chip Enable Truth Table ).
Read/Write Cycle Time
Address to Output Delay
CE
OE# to Output Delay
RP# High to Output Delay
CE
OE# to Output in Low Z
CE
OE# High to Output in High Z
Output Hold from Address, CE
Change, Whichever Occurs First
CE
BYTE# to Output Delay
BYTE# to Output in High Z
CEx Pulse width
Versions
X
X
X
X
to Output Delay
to Output in Low Z
High to Output in High Z
Low to BYTE# High or Low
CCQ
ELQV
= 2.7 V –3.6 V, and Transient Equivalent Testing Load Circuit for testing characteristics.
-t
Parameter
GLQV
0
, CE
after the first edge of CE
ELQV
1
, or CE
.
X
2
2.7 V—3.6V V
, or OE#
that enables the device. CE
5 V ± 10% V
32 Mbit
64 Mbit
32 Mbit
64 Mbit
32 Mbit
64 Mbit
32 Mbit
64 Mbit
0
, CE
Notes
CCQ
CCQ
1
2
2
2
3
3
3
3
3
3
3
3
, or CE
CCQ
(1)
= 5.0 V ±10%, Transient Input/Output
2
that enables the device (see Table 2, Chip
Min
100
150
–100/–150
–100/–150
10
X
0
0
0
high is defined at the first edge of CE
1000
1000
Max
100
150
100
150
180
210
50
55
15
10
PRELIMINARY
(4)
(4)
Min
120
10
0
0
0
–120
–120
(4)
(4)
1000
1000
Max
120
120
180
50
55
15
10
0
,