E28F320J5100 Intel, E28F320J5100 Datasheet - Page 45

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E28F320J5100

Manufacturer Part Number
E28F320J5100
Description
Manufacturer
Intel
Datasheet
NOTE:
C
AC test inputs are driven at V
(2.0 V
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35 V
(50% of V
L
Includes Jig Capacitance
Under Test
PRELIMINARY
Figure 15. Transient Equivalent Testing
TTL
Device
2.7
0.0
) and V
0.45
CCQ
2.4
). Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for V
Figure 14. Transient Input/Output Reference Waveform for V
IL
(0.8 V
Input
Input
Load Circuit
TTL
). Output timing ends at V
1.3V
OH
(2.4 V
R
L
1N914
C
INTEL
= 3.3 k
TTL
1.35
L
) for a Logic "1" and V
2.0
0.8
(Standard Testing Configuration)
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
Out
IH
and V
Test Points
Test Points
IL
. Input rise and fall times (10% to 90%) <10 ns.
OL
(0.45 V
V
V
Test Configuration Capacitance Loading Value
CCQ
CCQ
TTL
= 5.0 V
= 2.7 V 3.6 V
Test Configuration
) for a Logic "0." Input timing begins at V
10%
CCQ
CCQ
= 5.0 V ± 10%
= 2.7 V 3.6 V
1.35
2.0
0.8
Output
Output
C
L
100
50
(pF)
IH
45

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