E28F320J5100 Intel, E28F320J5100 Datasheet - Page 38

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

INTEL
38
FULL STATUS CHECK PROCEDURE
Set Lock-Bit Complete
Block/Device Address
Block/Device Address
Read Status Register
Read Status Register
Data (See Above)
®
Check if Desired
Write 01H/F1H,
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
Set Lock-Bit
Successful
Write 60H,
Full Status
SR.4,5 =
SR. 1 =
SR.7 =
SR.3 =
SR.4 =
Start
0
0
0
0
1
0
1
1
1
1
Command Sequence
Voltage Range Error
Device Protect Error
Set Lock-Bit Error
Figure 11. Set Block Lock-Bit Flowchart
Error
Repeat for subsequent lock-bit operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations
Write FFH after the last lock-bit set operation to place device in read
array mode.
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command, in cases where multiple lock-bits are set before full
status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
Operation
Operation
Standby
Standby
Standby
Standby
Standby
Write
Write
Read
Bus
Bus
Set Block or Master
Set Block/Master
Lock-Bit Confirm
Command
Lock-Bit Setup
Command
Check SR.3
1 = Programming Voltage Error
Check SR.1
1 = Device Protect RP# = V
(set Block Lock-Bit Operation)
Check SR.4, 5
Both 1 = Command Sequence
Check SR.4
1 = Set Lock-Bit Error
PRELIMINARY
(Set Master Lock-Bit Operation)
RP# = V
Error
Detect
Data = 60H
Addr =Block Address (Block),
Data = 01H (Block)
Addr = Block Address (Block),
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
F1H (Master)
Device Address (Master)
Device Address (Master)
IH
, Master Lock-Bit Is Set
Comments
Comments
IH
0606_11