E28F320J5100 Intel, E28F320J5100 Datasheet - Page 41

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

The CUI latches commands issued by system
software and is not altered by V
CE
array mode upon power-up, after exit from
reset/power-down mode, or after V
below V
during V
After block erase, program, or lock-bit configuration,
even after V
must be placed in read array mode via the Read
Array command if subsequent access to the
memory array is desired. V
below V
5.5
The device is designed to offer protection against
accidental block erasure, programming, or lock-bit
configuration during power transitions. Internal
circuitry resets the CUI to read array mode at
power-up.
2
PRELIMINARY
transitions, or WSM actions. Its state is read
CC
CC
LKO
Power-Up/Down Protection
during V
transitions.
. V
PEN
CC
transitions down to V
must be kept at or above V
PEN
transitions.
PEN
INTEL
must be kept at or
PEN
, CE
PENLK
CC
®
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
transitions
0
, CE
, the CUI
1
, or
PEN
A system designer must guard against spurious
writes for V
active. Since WE# must be low and the device
enabled (see Table 2, Chip Enable Truth Table ) for
a command write, driving WE# to V
the device will inhibit writes. The CUI’s two-step
command sequence architecture provides added
protection against data alteration.
Keeping V
data alteration. In-system block lock and unlock
capability protects the device against inadvertent
programming. The device is disabled while RP# =
V
5.6
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory’s nonvolatility
increases usable battery life because data is
retained when system power is removed.
IL
regardless of its control inputs.
Power Dissipation
PEN
CC
voltages above V
below V
PENLK
prevents inadvertent
LKO
IH
when V
or disabling
PEN
41
is