E28F320J5100 Intel, E28F320J5100 Datasheet - Page 50

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

INTEL
NOTES:
STS is shown in its default mode (RY/BY#).
NOTES:
1.
2.
3.
50
P1
P2
#
These specifications are valid for all product versions (packages and speeds).
If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum
required RP# Pulse Low Time is 100 ns.
A reset time, t
®
STS (R)
RP# (P)
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
t
t
Sym.
PLPH
PHRH
PHQV
RP# Pulse Low Time
(If RP# is tied to V
RP# High to Reset during Block Erase, Program, or
Lock-Bit Configuration
V
V
V
V
, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
IH
IH
IL
IL
Figure 18. AC Waveform for Reset Operation
CC
P1
, this specification is not applicable)
Parameter
Reset Specifications
P2
(1)
Notes
2
3
PRELIMINARY
Min
35
Max
100
Unit
µs
ns
0606_18