S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 100

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

Note:
1. Example DLP of 34h (or 00110100).
Note:
1. Example DLP of 34h (or 00110100).
100
10.4.8
Figure 10.41 DDR Fast Read Initial Access (4-byte Address, 0Eh or 0Dh [ExtAdd=1], EHPLC=01b)
DDR Dual I/O Read (BDh, BEh)
The instruction
 BDh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 BDh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 BEh is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, is shifted out, in a DDR fashion, two bits at a time on each
clock edge through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency by the rising and
falling edge of the SCK signal.
The DDR Dual I/O Read command improves throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is
similar to the Dual I/O Read command but transfers two address, mode, or data bits on every edge of the
clock. In some applications, the reduced instruction overhead might allow for code execution (XIP) directly
from the S25FL512S device.
The maximum operating clock frequency for DDR Dual I/O Read command is 66 MHz.
For DDR Dual I/O Read commands, there is a latency required after the last address bits are shifted into IO0
and IO1, before data begins shifting out of IO0 and IO1. There are different ordering part numbers that select
the latency code table used for this command, either the High Performance LC (HPLC) table or the Enhanced
High Performance LC (EHPLC) table. The number of latency (dummy) clocks is determined by the frequency
Phase
Phase
Phase
SCK
SCK
CS#
CS#
Figure 10.43 DDR Fast Read Subsequent Access (4-byte Address, HPLC=01b)
SO
SCK
S O
CS#
SI
S I
S O
S I
7
Figure 10.42 Continuous DDR Fast Read Subsequent Access
7
31
Address
6
6
5
1 0 7 6 5 4 3 2 1 0
Instruction
5
4
Instruction
(4-byte Address [ExtAdd=1], EHPLC=01b)
4
3
3
D a t a
2
Mode
2
1
S25FL512S
0
1
S h e e t
Address
31
0
1 0 7 6 5 4 3 2 1 0
3.
Address
7 6 5 4
1 0
( P r e l i m i n a r y )
Mode
DLP
3 2 1 0
Dummy
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
DLP
7 6 5 4 3 2 1 0 7 6
S25FL512S_00_04 June 13, 2012
7 6 5 4 3 2 1 0 7 6
Data 1
Data 1
Data 1
D2
D 2
D 2