S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 113
![no-image](/images/no-image-200.jpg)
S25FL512SAGMFIG13
Manufacturer Part Number
S25FL512SAGMFIG13
Description
Flash 512Mb 3V 133MHz Serial NOR Flash
Manufacturer
Spansion
Datasheet
1.S25FL512SAGMFI011.pdf
(143 pages)
Specifications of S25FL512SAGMFIG13
Rohs
yes
Memory Type
Flash
Memory Size
512 MB
Architecture
Uniform
Timing Type
Asynchronous
Interface Type
SPI
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
SO-16
- Current page: 113 of 143
- Download datasheet (5Mb)
June 13, 2012 S25FL512S_00_04
The ASPP command affects the P_ERR and WIP bits of the Status and Configuration Registers in the same
manner as any other programming operation.
CS# input must be driven to the logic high state after the sixteenth bit of data has been latched in. If not, the
ASPP command is not executed. As soon as CS# is driven to the logic high state, the self-timed ASPP
operation is initiated. While the ASPP operation is in progress, the Status Register may be read to check the
value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a 1 during the self-timed ASPP
operation, and is a 0 when it is completed. When the ASPP operation is completed, the Write Enable Latch
(WEL) is set to a 0.
Phase
SCK
CS#
SO
SI
D a t a
7
6
S h e e t
5
Instruction
Figure 10.62 ASPP (2Fh) Command
4
3
2
( P r e l i m i n a r y )
1
S25FL512S
0
7
Input ASPR Low Byte
6
5
4
3
2
1
0
7
Input ASPR High Byte
6
5
4
3
2
1
0
113
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