S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 57

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

June 13, 2012 S25FL512S_00_04
8.6.2
Configuration Register 1 (CR1)
Block Protection (BP2, BP1, BP0) SR1[4:2]: These bits define the main flash array area to be software-
protected against program and erase commands. The BP bits are either volatile or non-volatile, depending on
the state of the BP non-volatile bit (BPNV) in the configuration register. When one or more of the BP bits is set
to 1, the relevant memory area is protected against program and erase. The Bulk Erase (BE) command can
be executed only when the BP bits are cleared to 0’s. See
how the BP bit values select the memory array area protected. The BP bits have the same non-volatile
endurance as the main flash array.
Write Enable Latch (WEL) SR1[1]: The WEL bit must be set to 1 to enable program, write, or erase
operations as a means to provide protection against inadvertent changes to memory or register values. The
Write Enable (WREN) command execution sets the Write Enable Latch to a 1 to allow any program, erase, or
write commands to execute afterwards. The Write Disable (WRDI) command can be used to set the Write
Enable Latch to a 0 to prevent all program, erase, and write commands from execution. The WEL bit is
cleared to 0 at the end of any successful program, write, or erase operation. Following a failed operation the
WEL bit may remain set and should be cleared with a WRDI command following a CLSR command. After a
power down/power up sequence, hardware reset, or software reset, the Write Enable Latch is set to a 0 The
WRR command does not affect this bit.
Write In Progress (WIP) SR1[0]: Indicates whether the device is performing a program, write, erase
operation, or any other operation, during which a new operation command will be ignored. When the bit is set
to a 1 the device is busy performing an operation. While WIP is 1, only Read Status (RDSR1 or RDSR2),
Erase Suspend (ERSP), Program Suspend (PGSP), Clear Status Register (CLSR), and Software Reset
(RESET) commands may be accepted. ERSP and PGSP will only be accepted if memory array erase or
program operations are in progress. The status register E_ERR and P_ERR bits are updated while WIP = 1.
When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains
busy and unable to receive new operation commands. A Clear Status Register (CLSR) command must be
received to return the device to standby mode. When the WIP bit is cleared to 0 no operation is in progress.
This is a read-only bit.
Related Commands: Read Configuration Register (RDCR 35h), Write Registers (WRR 01h). The
Configuration Register bits can be changed using the WRR command with sixteen input cycles.
The configuration register controls certain interface and data protection functions.
Bits
7
6
5
4
3
2
1
0
Field Name
D a t a
TBPROT
FREEZE
QUAD
BPNV
RFU
RFU
LC1
LC0
S h e e t
Register, TBPROT in
Lock current state of
Configures BP2-0 in
Puts the device into
BP2-0 bits in Status
Quad I/O operation
Configures Start of
Register, and OTP
Block Protection
Status Register
Latency Code
Configuration
Function
regions
RFU
RFU
( P r e l i m i n a r y )
Table 8.4 Configuration Register (CR1)
S25FL512S
Non-Volatile
Non-Volatile
Volatile
Type
OTP
OTP
RFU
RFU
Default
State
0
0
0
0
0
0
0
0
Block Protection on page 65
Selects number of initial read latency cycles
See Latency Code Tables
1 = BP starts at bottom (Low address)
0 = BP starts at top (High address)
Reserved for Future Use
1 = Volatile
0 = Non-Volatile
Reserved for Future Use
1 = Quad
0 = Dual or Serial
1 = Block Protection and OTP locked
0 = Block Protection and OTP un-locked
Description
for a description of
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