S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 96

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

96
 EBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 ECh is followed by a 4-byte address (A31-A0)
The Quad I/O Read command improves throughput with four I/O signals — IO0-IO3. It is similar to the Quad
Output Read command but allows input of the address bits four bits per serial SCK clock. In some
applications, the reduced instruction overhead might allow for code execution (XIP) directly from the
S25FL512S device. The QUAD bit of the Configuration Register must be set (CR Bit1=1) to enable the Quad
capability of the S25FL512S device.
The maximum operating clock frequency for Quad I/O Read is 104 MHz.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before
data begins shifting out of IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal
circuitry enough time to access data at the initial address. During latency cycles, the data value on IO0-IO3
are “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of
SCK and the latency code table (refer to
on page
command, either the High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC)
table. The number of dummy cycles is set by the LC bits in the Configuration Register (CR1). However, both
latency code tables use the same latency values for the Quad I/O Read command.
Following the latency period, the memory contents at the address given, is shifted out four bits at a time
through IO0-IO3. Each nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK
signal.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled
through the setting of the Mode bits (after the address sequence, as shown in
Figure 10.37 on page
improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next
Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits
3-0) of the Mode bits are “don’t care” (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O
High Performance Read Mode and the next address can be entered (after CS# is raised high and then
asserted low) without requiring the EBh or ECh instruction, as shown in
Figure 10.38 on page
will release the device from Quad I/O High Performance Read mode; after which, the device can accept
standard SPI commands:
During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0-IO3) are
not set for a valid instruction sequence, then the device will be released from Quad I/O High Performance
Read mode. Note that the two mode bit clock cycles and additional wait states (i.e., dummy cycles) allow the
device’s internal circuitry latency time to access the initial address after the last address cycle that is clocked
into IO0-IO3.
It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data
out clock. At higher clock speeds the time available to turn off the host outputs before the memory device
begins to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing IO0-IO3 signal
contention, for the host system to turn off the IO0-IO3 signal outputs (make them high impedance) during the
last “don’t care” mode cycle or during any dummy cycles.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
1. During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh,
then the next time CS# is raised high the device will be released from Quad I/O High Performance
Read mode.
59). There are different ordering part numbers that select the latency code table used for this
98; thus, eliminating eight cycles for the command sequence. The following sequences
97). This added feature removes the need for the instruction sequence and greatly
D a t a
S25FL512S
Table 8.7, Latency Codes for SDR Enhanced High Performance
S h e e t
( P r e l i m i n a r y )
Figure 10.36 on page 97
S25FL512S_00_04 June 13, 2012
Figure 10.35 on page 97
or
or