S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 94

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

94
For the Dual I/O Read command, there is a latency required after the last address bits are shifted into SI and
SO before data begins shifting out of IO0 and IO1. There are different ordering part numbers that select the
latency code table used for this command, either the High Performance LC (HPLC) table or the Enhanced
High Performance LC (EHPLC) table. The HPLC table does not provide cycles for mode bits so each Dual I/
O Read command starts with the 8 bit instruction, followed by address, followed by a latency period.
This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the
initial address. During the dummy cycles, the data value on SI and SO are “don’t care” and may be high
impedance. The number of dummy cycles is determined by the frequency of SCK
for SDR Enhanced High Performance on page
Configuration Register (CR1).
The EHPLC table does provide cycles for mode bits so a series of Dual I/O Read commands may eliminate
the 8-bit instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the
following command will also be a Dual I/O Read command. The first Dual I/O Read command in a series
starts with the 8-bit instruction, followed by address, followed by four cycles of mode bits, followed by a
latency period. If the mode bit pattern is Axh the next command is assumed to be an additional Dual I/O Read
command that does not provide instruction bits. That command starts with address, followed by mode bits,
followed by latency.
The Enhanced High Performance feature removes the need for the instruction sequence and greatly
improves code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual
I/O Read command through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits
3-0) of the Mode bits are “don’t care” (“x”) and may be high impedance. If the Mode bits equal Axh, then the
device remains in Dual I/O Enhanced High Performance Read Mode and the next address can be entered
(after CS# is raised high and then asserted low) without the BBh or BCh instruction, as shown in
Figure
the device from Dual I/O Enhanced High Performance Read mode; after which, the device can accept
standard SPI commands:
During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0 and IO1)
are not set for a valid instruction sequence, then the device will be released from Dual I/O Enhanced High
Performance Read mode. Note that the four mode bit cycles are part of the device’s internal circuitry latency
time to access the initial address after the last address cycle that is clocked into IO0 (SI) and IO1 (SO).
It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out
clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins
to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing I/O signal contention,
for the host system to turn off the I/O signal outputs (make them high impedance) during the last two “don’t
care” mode cycles or during any dummy cycles.
Following the latency period the memory content, at the address given, is shifted out two bits at a time
through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK
signal.
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
1. During the Dual I/O Enhanced High Performance Command Sequence, if the Mode bits are any
10.34; thus, eliminating eight cycles for the command sequence. The following sequences will release
value other than Axh, then the next time CS# is raised high the device will be released from Dual
I/O Read Enhanced High Performance Read mode.
D a t a
S25FL512S
S h e e t
59). The number of dummy cycles is set by the LC bits in the
( P r e l i m i n a r y )
S25FL512S_00_04 June 13, 2012
(Table 8.7, Latency Codes