S25FL512SAGMFIG13 Spansion, S25FL512SAGMFIG13 Datasheet - Page 64

• Manufacturer Part Number: S25FL512SAGMFIG13
• Description: Flash 512Mb 3V 133MHz Serial NOR Flash
• Manufacturer: Spansion

Specifications of S25FL512SAGMFIG13

• Rohs: yes
• Memory Type: Flash
• Memory Size: 512 MB
• Architecture: Uniform
• Timing Type: Asynchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SO-16

9.
9.1
9.2
64
9.1.1
9.1.2
9.1.3
9.1.4
Data Protection
Secure Silicon Region (OTP)
Write Enable Command
Reading OTP Memory Space
Programming OTP Memory Space
Spansion Programmed Random Number
Lock Bytes
The device has a 1024-byte One Time Program (OTP) address space that is separate from the main flash
array. The OTP area is divided into 32, individually lockable, 32-byte aligned and length regions.
The OTP memory space is intended for increased system security. OTP values can “mate” a flash
component with the system CPU/ASIC to prevent device substitution. See
One Time Program Array Commands on page
The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 1-kB
OTP address range will yield indeterminate data.
The protocol of the OTP programming command is the same as Page Program. The OTP Program command
can be issued multiple times to any given OTP address, but this address space can never be erased. The
valid address range for OTP Program is depicted in
Program operations outside the valid OTP address range will be ignored and the WEL in SR1 will remain high
(set to 1). OTP Program operations while FREEZE = 1 will fail with P_ERR in SR1 set to 1.
Spansion standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to
0xF) with a 128-bit random number using the Linear Congruential Random Number Method. The seed value
for the algorithm is a random number concatenated with the day and time of tester insertion.
The LSB of each Lock byte protects the lowest address region related to the byte, the MSB protects the
highest address region related to the byte. The next higher address byte similarly protects the next higher 8
regions. The LSB bit of the lowest address Lock Byte protects the higher address 16 bytes of the lowest
address region. In other words, the LSB of location 0x10 protects all the Lock Bytes and RFU bytes in the
lowest address region from further programming. See
The Write Enable (WREN) command must be written prior to any command that modifies non-volatile data.
The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to 0 (disables writes)
during power-up, hardware reset, or after the device completes the following commands:
– Reset
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Registers (WRR)
– Quad-input Page Programming (QPP)
– OTP Byte Programming (OTPP)
D a t a
S25FL512S
S h e e t
111, and
Figure 8.1, OTP Address Space on page
( P r e l i m i n a r y )
Section 8.5, OTP Address Space on page
OTP Read (OTPR 4Bh): on page
OTP Address Space on page
S25FL512S_00_04 June 13, 2012
112.
55. OTP
54.
54,