PCAL6416APW,118 NXP Semiconductors, PCAL6416APW,118 Datasheet
PCAL6416APW,118
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PCAL6416APW,118 Summary of contents
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PCAL6416A Low-voltage translating 16-bit I with interrupt output, reset, and configuration registers Rev. 3 — 24 December 2012 1. General description The PCAL6416A is a 16-bit general purpose I/O expander that provides remote I/O expansion for most microcontroller families via ...
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... NXP Semiconductors The system master can reset the PCAL6416A in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the I causes the same reset/initialization to occur without depowering the part. ...
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... NXP Semiconductors Latched outputs with 25 mA drive maximum capability for directly driving LEDs Latch-up performance exceeds 100 mA per JESD 78, Class II ESD protection exceeds JESD 22 2000 V Human-Body Model (A114-A) 1000 V Charged-Device Model (C101) Packages offered: TSSOP24, HVQFN24, VFBGA24, XFBGA24 2.1 Agile I/O features ...
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... Ordering options Table 2. Ordering options Type number Orderable part number PCAL6416AEV PCAL6416AEVJ PCAL6416AEX <tbd> PCAL6416AHF PCAL6416AHF,128 PCAL6416APW PCAL6416APW,118 4. Block diagram Fig 1. PCAL6416A Product data sheet Low-voltage translating 16-bit I Package Packing method VFBGA24 Reel pack, SMD, 13-inch XFBGA24 Reel pack, SMD, 7-inch ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Fig 4. PCAL6416A Product data sheet Low-voltage translating 16-bit I PCAL6416APW 002aaf963 Pin configuration for TSSOP24 PCAL6416AEV 002aaf966 Pin configuration for VFBGA24 (3 mm 3 mm) All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 December 2012 ...
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... NXP Semiconductors Fig 6. PCAL6416A Product data sheet Low-voltage translating 16-bit I PCAL6416AEX 002aah190 Pin configuration for XFBGA24 (2 mm 2 mm) All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 December 2012 PCAL6416A 2 C-bus/SMBus I/O expander An empty cell indicates no ball is populated at that grid point. ...
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... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin TSSOP24 HWQFN24 INT DD(I2C-bus) RESET 3 24 [1] P0_0 4 1 [1] P0_1 5 2 [1] P0_2 6 3 [1] P0_3 7 4 [1] P0_4 8 5 [1] P0_5 9 6 [1] P0_6 10 7 [1] P0_7 [2] P1_0 13 10 [2] P1_1 14 11 [2] P1_2 15 12 ...
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... NXP Semiconductors 6. Voltage translation Table C-bus and the PCAL6416A. Table 4. V DD(I2C-bus) 1.8 V 1.8 V 1.8 V 1.8 V 2.5 V 2.5 V 2.5 V 2.5 V 3.3 V 3.3 V 3 PCAL6416A Product data sheet Low-voltage translating 16-bit I shows how to set up V levels for the necessary voltage translation between the ...
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... NXP Semiconductors 7. Functional description Refer to 7.1 Device address The address of the PCAL6416A is shown in Fig 8. ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW (logic 0) to assign one of the two possible slave addresses. The last bit of the slave address (R/W) defines the operation (read or write performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation ...
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... NXP Semiconductors Table 6. Command byte Pointer register bits ...
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... NXP Semiconductors 7.4 Register descriptions 7.4.1 Input port register pair (00h, 01h) The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port registers are read only; writes to these registers have no effect. ...
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... NXP Semiconductors 7.4.3 Polarity inversion register pair (04h, 05h) The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register bit in these registers is set (written with ‘1’), the corresponding port pin’s polarity is inverted in the input register bit in this register is cleared (written with a ‘ ...
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... NXP Semiconductors 7.4.5 Output drive strength register pairs (40h, 41h, 42h, 43h) The Output drive strength registers control the output drive level of the GPIO. Each GPIO can be configured independently to a certain output current level by two register control bits. For example Port 0.7 is controlled by register 41 CC0.7 (bits [7:6]), Port 0.6 is controlled by register 41 CC0.6 (bits [5:4]). The output drive level of the GPIO is programmed 00b = 0.25 ...
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... NXP Semiconductors cleared, assuming there were no additional input(s) that have changed, and bit 4 of the input port 0 register will read ‘1’. The next read of the input port register bit 4 register should now read ‘0’. An interrupt remains active when a non-latched input simultaneously switches state with a latched input and then returns to its original state ...
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... NXP Semiconductors 7.4.8 Pull-up/pull-down selection register pair (48h, 49h) The I/O port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that I/O pin. If the pull-up/down feature is disconnected, writing to this register will have no effect on I/O pin. Typical value is 100 k ...
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... NXP Semiconductors 7.4.10 Interrupt status register pair (4Ch, 4Dh) These read-only registers are used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt. ...
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... NXP Semiconductors Fig 10. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7) 7.6 Power-on reset When power (from applied to V PCAL6416A in a reset condition until V condition is released and the PCAL6416A registers and I initializes to their default states. After that, V back up to the operating voltage for a power-reset cycle. See requirements” ...
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... NXP Semiconductors 7.8 Interrupt output (INT) An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After time t changes back to the original value or when data is read from the port that generated the interrupt (see or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse ...
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Fig 11. Write to Output port register Fig 12. Write to device registers 002aaf556 002aag972 ...
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... NXP Semiconductors 8.2 Read commands To read data from the PCAL6416A, the bus master must first send the PCAL6416A address with the least significant bit set to a logic 0 (see The command byte is sent after the address and determines which register accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1 ...
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Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode assumed that the command byte has previously been set to ...
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Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode assumed that the command byte has previously been set to ...
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Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode assumed that the command byte has previously been set to ...
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... NXP Semiconductors 9. Application design-in information Device address configured as 0100 000x for this example. P0_0 and P0_2 through P1_0 are configured as inputs. P0_1 and P1_1 through P1_7 are configured as outputs. (1) External resistors are required for inputs (on P port) that may float. Also, internal pull-up or pull-down may be used to eliminate the need for external components ...
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... NXP Semiconductors Fig 18. High value resistor in parallel with 9.2 Output drive strength control The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels. By programming these bits the user is changing the number of transistor pairs or ‘ ...
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... NXP Semiconductors Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through V and will create noise (some radiated, but more critically Simultaneous Switching Noise (SSN)) ...
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... NXP Semiconductors Table 30. Recommended supply sequencing and ramp rates (unless otherwise noted). Not tested; specified by design. amb Symbol Parameter (dV/dt) fall rate of change of voltage f (dV/dt) rise rate of change of voltage r t reset delay time d(rst) V glitch supply voltage difference DD(gl) t supply voltage glitch pulse width ...
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... NXP Semiconductors 9.4 Device current consumption with internal pull-up and pull-down resistors The PCAL6416A integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. ...
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... NXP Semiconductors more clocks ensures the slave state machine returns to a known, idle state since the protocol calls for eight data bits and one ACK bit. It does not matter when the slave state machine finishes its transmission, extra clocks will be recognized as STOP conditions. ...
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... NXP Semiconductors 11. Recommended operating conditions Table 32. Operating conditions Symbol Parameter C-bus supply voltage DD(I2C-bus) V supply voltage port P DD(P) V HIGH-level input voltage IH V LOW-level input voltage IL I HIGH-level output current OH I LOW-level output current OL T ambient temperature amb 12. Thermal characteristics Table 33. ...
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... NXP Semiconductors 13. Static characteristics Table 34. Static characteristics + amb DD(I2C-bus) Symbol Parameter V input clamping voltage IK V power-on reset voltage POR V HIGH-level output OH [2] voltage V LOW-level OL [2] output voltage I LOW-level OL [3] output current I input current I I HIGH-level input current P port; V ...
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... NXP Semiconductors Table 34. Static characteristics + amb DD(I2C-bus) Symbol Parameter I supply current DD I additional quiescent DD [5] supply current C input capacitance i C input/output capacitance internal pull-up pu(int) resistance R internal pull-down pd(int) resistance PCAL6416A Product data sheet Low-voltage translating 16-bit I … ...
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... NXP Semiconductors [1] For I , all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3 typical values are DD(P) DD(I2C-bus) [2] The total current sourced by all I/Os must be limited to 160 mA. [3] Each I/O must be externally limited to a maximum and each octal (P0_0 to P0_7 and P1_0 to P1_7) must be limited to a maximum current of 100 mA, for a device total of 200 mA ...
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... NXP Semiconductors 1.65 V DD( 2.5 V DD( 5.0 V DD(P) Fig 29. I/O sink current versus LOW-level output voltage with CCX.X = 11b PCAL6416A Product data sheet Low-voltage translating 16-bit I 002aaf578 b. V DD(P) 002aaf580 d. V DD(P) 002aaf582 f. V DD(P) All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 December 2012 ...
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... NXP Semiconductors 1.65 V DD( 2.5 V DD( 5.0 V DD(P) Fig 30. I/O source current versus HIGH-level output voltage with CCX.X = 11b PCAL6416A Product data sheet Low-voltage translating 16-bit I 002aaf561 b. V DD(P) 002aaf563 d. V DD(P) 002aaf565 f. V DD(P) All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 December 2012 ...
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... NXP Semiconductors ( 1 DD(P) sink ( DD(P) sink ( 1 DD(P) sink ( DD(P) sink Fig 31. LOW-level output voltage versus temperature with CCX.X = 11b PCAL6416A Product data sheet Low-voltage translating 16-bit I 002aah056 I source Fig 32. I/O high voltage versus temperature with CCX ...
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... NXP Semiconductors 14. Dynamic characteristics 2 Table 35. I C-bus interface timing requirements Over recommended operating free air temperature range, unless otherwise specified. See Symbol Parameter f SCL clock frequency SCL t HIGH period of the SCL clock HIGH t LOW period of the SCL clock LOW t pulse width of spikes that must ...
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... NXP Semiconductors Table 37. Switching characteristics Over recommended operating free air temperature range; C Symbol Parameter t valid time on pin INT v(INT) t reset time on pin INT rst(INT) t data output valid time v(Q) t data input set-up time su(D) t data input hold time h(D) 15. Parameter measurement information a. SDA load configuration b ...
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... NXP Semiconductors a. Interrupt load configuration b. Voltage waveforms C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z All parameters and waveforms are not applicable to all devices. Fig 34. Interrupt load circuit and voltage waveforms PCAL6416A ...
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... NXP Semiconductors a. P port load configuration b. Write mode (R Read mode (R includes probe and jig capacitance measured from 0.7 v(Q) All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. ...
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... NXP Semiconductors a. SDA load configuration c. RESET timing C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time, with one transition per measurement. I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices. ...
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... NXP Semiconductors 16. Package outline HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 0.75 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0.30 mm 0.8 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors VFBGA24: plastic very thin fine-pitch ball grid array package; 24 balls; body 0.85 mm Fig 39. Package outline SOT1199-1 (VFBGA24) PCAL6416A Product data sheet Low-voltage translating 16-bit I All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 December 2012 PCAL6416A 2 C-bus/SMBus I/O expander ...
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... NXP Semiconductors ;)%*$ SODVWLF H[WUHPHO\ WKLQ ILQHSLWFK EDOO JULG DUUD\ SDFNDJH EDOOV Fig 40. Package outline SOT1342-1 (XFBGA24) PCAL6416A Product data sheet Low-voltage translating 16-bit I All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 December 2012 PCAL6416A 2 C-bus/SMBus I/O expander 627 VRWBSR © ...
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... NXP Semiconductors 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 41. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCAL6416A Product data sheet Low-voltage translating 16-bit I maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...
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... NXP Semiconductors 18. Soldering: PCB footprints Footprint information for reflow soldering of TSSOP24 package solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 42. PCB footprint for SOT355-1 (TSSOP24); reflow soldering PCAL6416A Product data sheet Low-voltage translating 16-bit I ...
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... NXP Semiconductors Footprint information for reflow soldering of HVQFN24 package (0.105 solder land solder paste deposit solder land plus solder paste occupied area Dimensions 0.500 5.000 5.000 3.200 3.200 07-09-24 Issue date 09-06-15 Fig 43. PCB footprint for SOT994-1 (HWQFN24); reflow soldering ...
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... NXP Semiconductors 19. Abbreviations Table 40. Acronym ESD FET GPIO 2 I C-bus I/O LED LSB MSB PCB POR SMBus 20. Revision history Table 41. Revision history Document ID Release date PCAL6416A v.3 20121224 • Modifications: Added XLBGA24 package option (PCAL6416AEX, SOT1342-1) PCAL6416A v.2 20121005 PCAL6416A v.1 20120808 PCAL6416A Product data sheet ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... PCAL6416A Product data sheet Low-voltage translating 16-bit I own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 3 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Voltage translation . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . . 9 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 Interface definition . . . . . . . . . . . . . . . . . . . . . . 9 7.3 Pointer register and command byte . . . . . . . . . 9 7.4 Register descriptions . . . . . . . . . . . . . . . . . . . 11 7 ...