PCAL6416APW,118 NXP Semiconductors, PCAL6416APW,118 Datasheet - Page 18

• Manufacturer Part Number: PCAL6416APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCAL6416APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 200 mA
• Output Current: 25 mA
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
8. Bus transactions
PCAL6416A
Product data sheet
7.8 Interrupt output (INT)
8.1 Write commands
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time t
changes back to the original value or when data is read from the port that generated the
interrupt (see
or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that
occur during the ACK or NACK clock pulse can be lost (or be very short) due to the
resetting of the interrupt during this pulse. Any change of the I/Os after resetting is
detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to V
V
of the device that requires the interrupt information.
When using the input latch feature, the input pin state is latched. The interrupt is reset only
when data is read from the port that generated the interrupt. The reset occurs in the
Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising
edge of the SCL signal.
The PCAL6416A is an I
PCAL6416A through write and read commands using I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
Data is transmitted to the PCAL6416A by sending the device address and setting the
Least Significant Bit (LSB) to a logic 0 (see
byte is sent after the address and determines which register receives the data that follows
the command byte.
Twenty-two registers within the PCAL6416A are configured to operate as eleven register
pairs. The eleven pairs are input port, output port, polarity inversion, configuration, output
drive strength (two 16-bit registers), input latch, pull-up/pull-down enable,
pull-up/pull-down selection, interrupt mask, and interrupt status registers. After sending
data to one register, the next data byte is sent to the other register in the pair (see
Figure 11
the next byte is stored in Output Port 0 (register 2).
There is no limit on the number of data bytes sent in one write transmission. In this way,
the host can continuously update a register pair independently of the other registers.
DD(I2C-bus)
and
v(INT)
, depending on the application. INT should be connected to the voltage source
Figure
Figure
, the signal INT is valid. The interrupt is reset when data on the port
All information provided in this document is subject to legal disclaimers.
16). Resetting occurs in the Read mode at the acknowledge (ACK)
12). For example, if the first byte is sent to Output Port 1 (register 3),
Rev. 3 — 24 December 2012
2
C-bus slave device. Data is exchanged between the master and
Low-voltage translating 16-bit I
Figure 8
for device address). The command
2
C-bus. The two communication
2
C-bus/SMBus I/O expander
PCAL6416A
© NXP B.V. 2012. All rights reserved.
DD(P)
or
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