PCAL6416APW,118 NXP Semiconductors, PCAL6416APW,118 Datasheet - Page 9

• Manufacturer Part Number: PCAL6416APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCAL6416APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 200 mA
• Output Current: 25 mA
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
7. Functional description
PCAL6416A
Product data sheet
7.1 Device address
7.2 Interface definition
7.3 Pointer register and command byte
Refer to
The address of the PCAL6416A is shown in
ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW
(logic 0) to assign one of the two possible slave addresses. The last bit of the slave
address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1)
selects a read operation, while a LOW (logic 0) selects a write operation.
Table 5.
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCAL6416A. The lower three
bits of this data byte state the operation (read or write) and the internal registers (Input,
Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in conjunction with
the lower three bits of the Command byte are used to point to the extended features of the
device (Agile IO). This register is write only.
Byte
I
I/O data bus
2
Fig 8.
Fig 9.
C-bus slave address
Figure 1 “Block diagram of PCAL6416A (positive
PCAL6416A address
Pointer register bits
Interface definition
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 December 2012
7 (MSB)
P0.7
P1.7
Low-voltage translating 16-bit I
L
P0.6
P1.6
H
6
P0.5
P1.5
5
L
Figure
P0.4
P1.4
4
L
8.
002aaf540
Bit
002aah045
P0.3
P1.3
logic)”.
3
L
2
C-bus/SMBus I/O expander
PCAL6416A
P0.2
P1.2
2
L
© NXP B.V. 2012. All rights reserved.
ADDR
P0.1
P1.1
1
0 (LSB)
P0.0
P1.0
R/W
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