PCAL6416APW,118 NXP Semiconductors, PCAL6416APW,118 Datasheet - Page 14

• Manufacturer Part Number: PCAL6416APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCAL6416APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 200 mA
• Output Current: 25 mA
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
PCAL6416A
Product data sheet
7.4.7 Pull-up/pull-down enable register pair (46h, 47h)
cleared, assuming there were no additional input(s) that have changed, and bit 4 of the
input port 0 register will read ‘1’. The next read of the input port register bit 4 register
should now read ‘0’.
An interrupt remains active when a non-latched input simultaneously switches state with a
latched input and then returns to its original state. A read of the input register reflects only
the change of state of the latched input and also clears the interrupt. The interrupt is not
cleared if the input latch register changes from latched to non-latched configuration.
If the input pin is changed from latched to non-latched input, a read from the input port
register reflects the current port logic level. If the input pin is changed from non-latched to
latched input, the read from the input register reflects the latched logic level. A register
pair write operation is described in
in
Table 19.
Table 20.
These registers allow the user to enable or disable pull-up/pull-down resistors on the I/O
pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting
the bit to logic 0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, the
resistors will be disconnected when the outputs are configured as open-drain outputs (see
Section
resistor. A register pair write operation is described in
operation is described in
Table 21.
Table 22.
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Section
7.4.11). Use the pull-up/pull-down registers to select either a pull-up or pull-down
8.2.
Input latch port 0 register (address 44h)
Input latch port 1 register (address 45h)
Pull-up/pull-down enable port 0 register (address 46h)
Pull-up/pull-down enable port 1 register (address 47h)
PE0.7
PE1.7
L0.7
L1.7
7
0
7
0
7
0
7
0
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 December 2012
PE0.6
PE1.6
L0.6
L1.6
6
0
6
0
6
0
6
0
Section
Low-voltage translating 16-bit I
PE0.5
PE1.5
L0.5
L1.5
8.2.
5
0
5
0
5
0
5
0
Section
PE0.4
PE1.4
L0.4
L1.4
8.1. A register pair read operation is described
4
0
4
0
4
0
4
0
PE0.3
PE1.3
L0.3
L1.3
Section
3
0
3
0
3
0
3
0
2
C-bus/SMBus I/O expander
PE0.2
PE1.2
8.1. A register pair read
L0.2
L1.2
PCAL6416A
2
0
2
0
2
0
2
0
© NXP B.V. 2012. All rights reserved.
PE0.1
PE1.1
L0.1
L1.1
1
0
1
0
1
0
1
0
PE0.0
PE1.0
L0.0
L1.0
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0
0
0
0
0
0
0
0