C8051F709-GQR Silicon Labs, C8051F709-GQR Datasheet - Page 262

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C8051F709-GQR

Manufacturer Part Number
C8051F709-GQR
Description
8-bit Microcontrollers - MCU 8kB 32B EEPROM Cap Sense
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F709-GQR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F709-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F70x/71x
33. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 3
offers the ability to be clocked from the external oscillator while the device is in Suspend mode, and can be
used as a wake-up source. This allows for implementation of a very low-power system, including RTC
capability.
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 33.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
clock source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
262
Timer 0 and Timer 1 Modes:
Two 8-bit counter/timers
8-bit counter/timer with
13-bit counter/timer
16-bit counter/timer
(Timer 0 only)
auto-reload
Two 8-bit timers with auto-reload
16-bit timer with auto-reload
Timer 2 Modes:
Rev. 1.0
Two 8-bit timers with auto-reload
16-bit timer with auto-reload
Timer 3 Modes:

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